VT82C596 Просмотр технического описания (PDF) - Unspecified

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VT82C596

PCI INTEGRATED PERIPHERAL CONTROLLER

Unspecified 

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LIST OF FIGURES

VT82C596B

FIGURE 1. PC SYSTEM CONFIGURATION USING THE VT82C596B ................................................................................. 3

FIGURE 2. VT82C596B BALL DIAGRAM (TOP VIEW)........................................................................................................... 4

FIGURE 3. VT82C596B PIN LIST (NUMERICAL ORDER)...................................................................................................... 5

FIGURE 4. VT82C596B PIN LIST (ALPHABETICAL ORDER)............................................................................................... 6

FIGURE 5. STRAP OPTION CIRCUIT....................................................................................................................................... 40

FIGURE 6. POWER MANAGEMENT SUBSYSTEM BLOCK DIAGRAM ........................................................................... 78

FIGURE 8. ULTRADMA-33 IDE TIMING - DRIVE INITIATING DMA BURST FOR READ COMMAND.................... 85

FIGURE 9. ULTRADMA-33 IDE TIMING - DRIVE INITIATING BURST FOR WRITE COMMAND............................ 85

FIGURE 10. ULTRADMA-33 IDE TIMING - PAUSING A DMA BURST ............................................................................. 86

FIGURE 11. ULTRADMA-33 IDE TIMING - DRIVE TERMINATING DMA BURST DURING READ COMMAND.... 87

FIGURE 12. ULTRADMA-33 IDE TIMING - DRIVE TERMINATING DMA BURST DURING WRITE COMMAND . 87

FIGURE 13. ULTRADMA-33 IDE TIMING - HOST TERMINATING DMA BURST DURING READ COMMAND...... 88

FIGURE 14. ULTRADMA-33 IDE TIMING - HOST TERMINATING DMA BURST DURING WRITE COMMAND ... 88

FIGURE 15. ULTRADMA-33 IDE TIMING - PIO CYCLE ...................................................................................................... 89

FIGURE 16. MECHANICAL SPECIFICATIONS - 324-PIN BALL GRID ARRAY PACKAGE ......................................... 90

LIST OF TABLES

TABLE 1. PIN DESCRIPTIONS..................................................................................................................................................... 7

TABLE 2. SYSTEM I/O MAP ....................................................................................................................................................... 21

TABLE 3. REGISTERS.................................................................................................................................................................. 21

TABLE 4. KEYBOARD CONTROLLER COMMAND CODES .............................................................................................. 31

TABLE 5. CMOS REGISTER SUMMARY................................................................................................................................. 34

TABLE 6. AC CHARACTERISTICS - PCI CYCLE TIMING.................................................................................................. 83

TABLE 7. AC CHARACTERISTICS - ULTRADMA-33 IDE BUS INTERFACE TIMING.................................................. 84

Revision 0.3 June 17, 1999

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