VSC7135 Просмотр технического описания (PDF) - Vitesse Semiconductor

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VSC7135

1.25Gbits/sec Gigabit Ethernet Transceiver

Vitesse Semiconductor 

VITESSE

SEMICONDUCTOR CORPORATION

1.25Gbits/sec

Gigabit Ethernet Transceiver

RCLK

Figure 5: Receive Timing Waveforms

T4

T3

Data Sheet

VSC7135

RCLKN

R0:9

Data Valid

T1

T2

Data Valid

Data Valid

Table 2: Receive AC Characteristics

Parameters

T1

T2

T3

T4

Description

Data or COM_DET Valid

prior to RCLK/RCLKN

rise

Data or COM_DET Valid

after RCLK or RCLKN

rise

Deviation of RCLK

rising edge to RCLKN

rising edge delay from

nominal.

delay=

-f---b---a--u---d-

10

±

T3

Deviation of RCLK,

RCLKN frequency from

nominal.

f RCLK=

-f---R---E----F---C---L---K--

2

±

T4

Min.

3.0

2.0

-500

-1.0

Max. Units

Conditions

—

ns. Measured between the 1.4V

point of RCLK or RCLKN

and a valid level of R0:9. All

—

ns. outputs driving 10pF load.

500

ps.

Nominal delay is 10 bit times.

Tested on sample basis

Whether or not locked to

1.0

% serial data

TR, TF

Rlat

TLOCK

Tjtd

Djtd

R0:9, COM_DET, RCLK,

RCLKN rise and fall time

—

2.4

ns.

Between Vil(max) and Vih(min),

into 10 pf. load.

Latency from RX to R0:9 15bc + 2ns 34bc + 2ns

bc = Bit clock

ns = Nano second

Data acquisition lock time

@ 1.25 Gb/s

—

2.0

µs.

8B/10B IDLE pattern.

Tested on a sample basis

Total receive data jitter

tolerance (p-p)

599

ps

IEEE 802.3Z Clause 38.68,

tested on a sample basis

Total deterministic data

jitter tolerance (p-p)

370

ps

IEEE 802.3Z Clause 38.69,

tested on a sample basis

NOTE: Probability of Recovery for data acquisition is 95% per section 5.3 of the FC-PH rev. 4.3.

Page 6

© VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

G52146-0, Rev. 4.0

5/28/98

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