VRS51L1050-25-Q Просмотр технического описания (PDF) - Ramtron International Corporation
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VRS51L1050-25-Q Datasheet PDF : 49 Pages
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VRS51L1050
VRS51L1050 DIP-40 Pin Descriptions
TABLE 2: VRS51L1050 PIN DESCRIPTIONS FOR DIP40 PACKAGE
DIP40 Name I/O
Function
1
T2
P1.0
I
Timer 2 Clock Out
I/O Bit 0 of Port 1
2
T2EX
P1.1
I
Timer 2 Control
I/O Bit 1 of Port 1
PWM0
PWM Channel 0
3
P1.2
I/O Bit 2 of Port 1
4
PWM1
P1.3
O PWM Channel 1
I/O Bit 3 of Port 1
5
P1.4
I/O Bit 4 of Port 1
6
P1.5
I/O Bit 5 of Port 1
7
SCL
P1.6
O I²C SCL
I/O Bit 6 of Port 1
8
SDA
P1.7
O I²C SDA
I/O Bit 7 of Port 1
9
RESET I
Reset
10
RXD
P3.0
I
Receive Data
I/O Bit 0 of Port 3
11
TXD
P3.1
O Transmit Data &
I/O Bit 1 of Port 3
12
#INT0
P3.2
I
External Interrupt 0
I/O Bit 2 of Port 3
13
#INT1
P3.3
I
External Interrupt 1
I/O Bit 3 of Port 3
14
T0
P3.4
I
Timer 0
I/O Bit 4 of Port 3
15
T1
P3.5
I
Timer 1 & 3
I/O Bit 5 of Port
16
#WR
P3.6
O Ext. Memory Write
I/O Bit 6 of Port 3
17
#RD
P3.7
O Ext. Memory Read
I/O Bit 7 of Port 3
18 XTAL2 O Oscillator/Crystal Output
19 XTAL1 I
Oscillator/Crystal In
20 VSS
-
Ground
T2 / P1.0
T2EX / P1.1
PWM0 / P1.2
PWM1 / P1.3
P1.4
P1.5
SCL / P1.6
SDA / P1.7
RESET
RXD / P3.0
TXD / P3.1
#INT0 / P3.2
#INT1 / P3.3
T0 / P3.4
T1 / P3.5
#WR / P3.6
#RD / P3.7
XTAL2
XTAL1
VSS
1
40
2
39
3
38
4
37
5
36
6
35
7
34
8
33
9
32
VRS51L1050
10
31
DIP-40
11
30
12
29
13
28
14
27
15
26
16
25
17
24
18
23
19
22
20
21
VDD
P0.0 / AD0
P0.1 / AD1
P0.2 / AD2
P0.3 / AD3
P0.4 / AD4
P0.5 / AD5
P0.6 / AD6
P0.7 / AD7
#EA / VPP
ALE
PSEN
P2.7 / A15
P2.6 / A14
P2.5 / A13
P2.4 / A12
P2.3 / A11
P2.2 / A10
P2.1 / A9
P2.0 / A8
DIP40
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Name I/O
P2.0
I/O
A8
O
P2.1
I/O
A9
O
P2.2
I/O
A10
O
P2.3
I/O
A11
O
P2.4
I/O
A12
O
P2.5
I/O
A13
O
P2.6
I/O
A14
O
P2.7
I/O
A15
O
#PSEN O
ALE
O
#EA /
VPP
I
P0.7
I/O
AD7
I/O
P0.6
I/O
AD6
I/O
P0.5
I/O
AD5
I/O
P0.4
I/O
AD4
I/O
P0.3
I/O
AD3
I/O
P0.2
I/O
AD2
I/O
P0. 1 I/O
AD1
I/O
P0.0
I/O
AD0
I/O
VDD
-
Function
Bit 0 of Port 2
Bit 8 of External Memory Address
Bit 1 of Port 2
Bit 9 of External Memory Address
Bit 2 of Port 2
Bit 10 of External Memory Address
Bit 3 of Port 2 &
Bit 11 of External Memory Address
Bit 4 of Port 2
Bit 12 of External Memory Address
Bit 5 of Port 2
Bit 13 of External Memory Address
Bit 6 of Port 2
Bit 14 of External Memory Address
Bit 7 of Port 2
Bit 15 of External Memory Address
Program Store Enable
Address Latch Enable
External Access
Flash programming voltage input
Bit 7 Of Port 0
Data/Address Bit 7 of External
Memory
Bit 6 of Port 0
Data/Address Bit 6 of External
Memory
Bit 5 of Port 0
Data/Address Bit 5 of External
Memory
Bit 4 of Port 0
Data/Address Bit 4 of External
Memory
Bit 3 Of Port 0
Data/Address Bit 3 of External
Memory
Bit 2 of Port 0
Data/Address Bit 2 of External
Memory
Bit 1 of Port 0 & Data
Address Bit 1 of External Memory
Bit 0 Of Port 0 & Data
Address Bit 0 of External Memory
Supply input
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