VP2615CGGH1R Просмотр технического описания (PDF) - Mitel Networks

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производитель

VP2615CGGH1R

H.261 Decoder

Mitel Networks 

VP2615

WRITING DATA ONTO THE CBUS:

WRITING DATA FROM THE CBUS:

This diagram shows a typical instruction and associated data field being written to the device.

CEN

10ns

20ns

10ns

CADR

CSTR

CBUS

I/P

20ns

20ns

10ns

20ns

20ns

10ns

INSTRUCTION

20ns

20ns

10ns

20ns

20ns

10ns

DATA IN

READING INFORMATION ON CBUS :

This diagram shows a typical instruction and associated data field being read from the device.

CEN

CADR

CSTR

CBUS

20ns

20ns

10ns

Th

10ns

20ns

20ns

10ns

INSTRUCTION

20ns

50ns

10ns

10ns

20ns

20ns

20ns*

20ns*

10ns

20ns*

DATA OUT

If Th is less than 5 ns then CBUS may be driven by the VP2615until CEN going high eventually turns off

the drivers. It will not prevent correct data being read when CEN again goes active

N.B. All timings shown are minimum values except those marked * which are maximums.

Fig 7 : CBUS Timing

coded picture. As explained in the previous section, however,

it requires to be supplied with two macroblocks from the next

picture before a complete frame is fully decoded. The stand-

ard macroblock internal configuration is shown in Figure 5.

Output timing is shown in Figure 6. VPIX is toggled high

each time a valid pixel is available at the output pins, and

remains low when no pixel data is output. MBOUT is used to

define the boundaries between MacroBlocks, but is not used

when the device is directly connected to the VP520. The

Frame Ready Output nominally goes high on the same SYSCLK

edge as the first MBOUT goes high, and returns low when the

last MBOUT goes low. This will actually be after two macrob-

locks from the next frame have been supplied as inputs, but

this gap will not effect the operation of the VP520 which

converts macro block data to full resolution line data. The first

VPIX strobe produced after MBOUT goes high, will go high

after two SYSCLK periods, with the data being valid for two

SYSCLK periods either side of this edge. These delays are

subject to internal differential delays and will not be precise

clock period delays.

CBUS Control Port

The CBUS control port is used to input control and setup

information and also to output status information. In order to

save on pin count, a microprocessor driving this port is

required to execute two I/O instructions in order to transfer a

single byte of information to or from the device. The first

transfer is always a write operation, with a low level on the

single address line which is used by the interface. Data on the

bus then defines the instructions listed in Table 3. The second

transfer can be a read or write operation as necessary, but the

address line must then be high with the set up time given in

Figure 7.

In addition to the single addresss line (CADR), data

transfers use a control strobe (CSTR) which is only effective

6

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