VP2614CGGPFR Просмотр технического описания (PDF) - Mitel Networks

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VP2614CGGPFR

H.261 Video De-Multiplexer

Mitel Networks 

JTAG Test Interface

The VP2614 includes a test interface consisting of a

boundary scan loop of test registers placed between the pads

and the core of the chip. The control of this loop is fully JTAG/

IEEE 1149-1 1990 compatible. Please refer to this document

for a full description of the standard.

The interface has five dedicated pins: TMS, TDI, TDO,

TCK and TRST. The TRST pin is an independent reset for the

interface controller and should be pulsed low, soon after

power up; if the JTAG interface is not to be used it can be tied

low permanently. The TDI pin is the input for shifting in serial

instruction and test data; TDO the output for test data. The

TCK pin is the independent clock for the test interface and

registers, and TMS the mode select signal.

TDI and TMS are clocked in on the rising edge of TCK, and

all output transitions on TDO happen on its falling edge.

VP2614

Instructions are clocked into the 8 bit instruction register

(no parity bit) and the following instructions are available.

Instruction Register Name

( MSB first )

11111111

00000000

10XXXXXX

01XXXXXX

BYPASS

EXTEST (No inversion)

INTEST (Product test only)

SAMPLE/PRELOAD

The positions of the test registers in the boundary loop,

and their corresponding functional names, are detailed in

Table 3.

INTEST is non-standard and is used for production testing

and also to invoke the overall output enable function (TOE) via

the scan chain.

PIN FUNC

PIN FUNC PIN FUNC PIN FUNC PIN FUNC

1

N/C

21 GND

41

HD3

61

B1

81

A1

2

N/C

22 DCLK 42

HD4

62

B0

82

A0

3

N/C

23

LD

43

HD5

63

A14

83 BEN

4

TOE

24 PM0

44

HD6

64

A13

84 BCS

5

N/C

25 PM1

45

HD7

65

A12

85 GND

6 DMODE0 26

PM2

46

VDD

66

A11

86 VDD

7 DMODE1 27

N/C

47

GND

67

A10

87

WS

8 DMODE2 28

N/C

48

WR

68

A9

88 LRED

9 DMODE3 29

N/C

49

RD

69

A8

89

TDI

10

GND

30

N/C

50

CEN

70

A7

90 TMS

11

VDD

31 HA0

51

N/C

71

VDD

91 TRST

12 DBUS0

32

HA1

52

N/C

72

GND

92

TCK

13 DBUS1

33

HA2

53

B7

73

A6

93 TDO

14 DBUS2

34

HA3

54

B6

74

A5

94 VDD

15 DBUS3

35 SCLK

55

B5

75

A4

95 GND

16 DBUS4

36 GND

56

B4

76

A3

96 RES

17 DBUS5

37 VDD

57

B3

77

A2

97 LEN

18 DBUS6

38 HD0

58

B2

78

N/C

98 LCLK

19 DBUS7

39 HD1

59

GND

79

N/C

99 ERR

20

VDD

40 HD2

60

VDD

80

N/C

100 EVT

Table 2. Pinout

7

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