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HSP43220
(Rev.:2004)

Decimating Digital Filter

Intersil 

HSP43220

DDF Control Registers (Continued)

H_Register 2 (A1 = 1, A0 = 1)

RESERVED

H_GROWTH

H_STAGES

G5 G4 G3 G2 G1 G0 N2 N1 N0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

H_STAGES

Bits N0-N2 are used to select the number of stages or order of the

HDF filter. The number that is programmed in is equal to the

required number of stages. For a 5th order filter, H_STAGES

would be set equal to 5.

H_GROWTH

Bits G0-G5 are used to select the proper amount of growth bits.

H_GROWTH is calculated using the following equation:

H_GROWTH = 50 - CEILING {H_STAGES X log (HDEC)/ log(2)}

where the CEILING { } means use the next largest integer of the

result of the value in brackets and log is the log to the base 10.

The value of H_GROWTH represents the position of the LSB on

the output of the data shifter.

FIGURE 7.

Start Logic

The Start Logic generates a start signal that is used

internally to synchronously start the DDF. If ASTARTIN is

asserted (STARTIN must be tied high) the Start Logic

synchronizes it to CK_IN by double latching the signal and

generating the signal STARTOUT, which is shown in Figure

8. The STARTOUT signal is then used to synchronously

start other DDFs in a multi-chip configuration (the

STARTOUT signal of the first DDF would be tied to the

STARTIN of the second DDF). The NAND gate shown in

Figure 8 then passes this synchronized signal to be used on

chip to provide a synchronous start. Once started, the chip

requires a RESET to halt operation.

RESET

S

ASTARTIN D Q

S

DQ

STARTIN

ISTART

CK_IN

STARTOUT

FIGURE 8. START LOGIC

When STARTIN is asserted (ASTARTIN must be tied high)

the NAND gate passes STARTIN which is used to provide the

internal start, ISTART, for the DDF. When RESET is asserted

the internal start signal is held inactive, thus it is necessary to

assert either ASTARTIN or STARTIN in order to start the

DDF. The timing of the first valid DATA_IN with respect to

START_IN is shown in the Timing Waveforms.

In using ASTARTIN or STARTIN a high to low transition

must be detected by the rising edge of CK_IN, therefore

these signals must have been high for more than one CK_IN

cycle and then taken low.

The FIR Section

The second filter in the top level block diagram is a Finite

Impulse Response (FIR) filter which performs the final

shaping of the signal spectrum and suppresses the aliasing

components in the transition band of the HDF. This enables

the DDF to implement filters with narrow pass bands and

sharp transition bands.

The FIR is implemented in a transversal structure using a single

multiplier/accumulator (MAC) and RAM for storage of the data

and filter coefficients as shown in Figure 9. The FIR can

implement up to 512 symmetric taps and decimation up to 16.

The FIR is divided into 2 sections: the FIR filter section and

the FIR control logic.

Coefficient RAM

The Coefficient RAM stores the coefficients for the current FIR

filter being implemented. The coefficients are loaded into the

Coefficient RAM over the control bus (C_BUS). The

coefficients are written into the Coefficient RAM sequentially,

starting at location zero. It is only necessary to write one half

of the coefficients when symmetric filters are being

implemented, where the last coefficient to be written in is the

center tap.

8

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