HSP43220(2004) Просмотр технического описания (PDF) - Intersil
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HSP43220 Datasheet PDF : 18 Pages
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HSP43220
COMB_EN5
COMB_EN4
COMB_EN3
COMB_EN2
COMB_EN1
FROM
DECI-
MATION
REGISTER
RESET
REG
26
B A-B
A
22
RESET
REG
B A-B
A
21
RESET
REG
B A-B
19 A
20
RESET
REG
B A-B
A
19
RESET
REG
TO
ROUNDER
B A-B
A
CK_DEC
FIGURE 3. COMB FILTER
It is important to note that the Comb filter section has a speed
limitation. The Input sampling rate divided by the decimation
factor in the HDF (CK_IN/HDEC) should not exceed 4MHz.
Violating this condition causes the output of the filter to be
incorrect. When the HDF is put in bypass mode this limitation
does not apply. Equation 1 describes the relationship between
F_TAPS, F_DRATE, H_DRATE, CK_IN and FIR_CK.
Rounder
The filter accuracy is limited by the 16-bit data input. To
maintain the maximum accuracy, the output of the comb is
rounded to 16 bits.
The Rounder performs a symmetric round of the 19-bit
output of the last Comb stage. Symmetric rounding is done
to prevent the synthesis of a 0Hz spectral component by the
rounding process and thus causing a reduction in spurious
free dynamic range. Saturation logic is also provided to
prevent roll over from the largest positive value to the most
negative value after rounding. The output of the last comb
filter stage in the HDF section has a 16-bit integer portion
with a 3-bit fractional part in 2's complement format.
The rounding algorithm is as follows:
Clock Divider and Control Logic
The clock divider divides CK_IN by the decimation factor
HDEC to produce CK_DEC. CK_DEC clocks the Decimation
Register, Comb Filter section, HDF output register. In the
FIR filter CK_DEC is used to indicate that a new data
sample is available for processing. The clock generator is
cleared by RESET and is not enabled until the DDF is
started by an internal start signal (see Start Logic).
The Control Register Logic enables the updating of the Control
registers which contain all of the filter parameter data. When
WR and CS are asserted, the control register addressed by bits
A0 and A1 is loaded with the data on the C_BUS.
POSITIVE NUMBERS
Fractional Portion Greater Than or Equal to 0.5
Fractional Portion Less Than 0.5
NEGATIVE NUMBERS
Fractional Portion Less Than or Equal to 0.5
Fractional Portion Greater Than 0.5
Round Up
Truncate
Round Up
Truncate
The output of the rounder is latched into the HDF output
register with CK_DEC. CK_DEC is generated by the Clock
Divider section. The output of the register is cleared when
RESET is asserted.
5
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