V385A Просмотр технического описания (PDF) - Integrated Circuit Systems
Номер в каталоге
Компоненты Описание
производитель
V385A Datasheet PDF : 8 Pages
| |||
V385A
8-BIT LVDS TRANSMITTER FOR VIDEO
General Description
The V385A transmitter converts 28 bits of 3.3 V
CMOS/TTL into 4 Low Voltage Differential Signaling
(LVDS) data streams while the transmit clock input is
transmitted in parallel with the data streams over a fifth
LVDS link.
Compared to the V385, the V385A provides an
extended clock frequency range of 12-90 MHz, rather
than 20-85 MHz. Other performance improvements
have been incorporated as well.
The V385A can be programmed for rising edge or
falling edge clocks through pin R_FB.
Pin Assignment
VCC
TxIN5
TxIN6
TxIN7
GND
TxIN8
TxIN9
TxIN10
VCC
TxIN11
TxIN12
TxIN13
GND
TxIN14
TxIN15
TxIN16
R_FB
TxIN17
TxIN18
TxIN19
GND
TxIN20
TxIN21
TxIN22
TxIN23
VCC
TxIN24
TxIN25
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
56-pin TSSOP
TxIN4
TxIN3
TxIN2
GND
TxIN1
TxIN0
TxIN27
LVDS_GND
TxOUT0-
TxOUT0+
TxOUT1-
TxOUT1+
LVDS_VCC
LVDS_GND
TxOUT2-
TxOUT2+
TxCLKOUT-
TxCLKOUT+
TxOUT3-
TxOUT3+
LVDS_GND
PLL_GND
PLL_VCC
PLL_GND
PWRDWN
TxCLKIN
TxIN26
GND
Features
• Extended clock frequency range of 12 to 90 MHz
• Pin and function compatible with the National
DS90C385, TI SN65LVDS93 and THine
THC63LVDM83, but with extended clock frequency
and operating temperature range
• Convert 28 bits of 3.3 V CMOS/TTL into 4 LVDS
streams
• Up to 2.52 Gbps throughput or 315 Megabytes/sec
bandwidth
• Spread spectrum compatible
• Supports SD, HD and VGA graphics applications
• LVDS voltage swing of 350 mV for low EMI
• On-chip PLL requires no external components
• Single 3.3 V low-power CMOS design
• Operating temperature of 0 to +70°C
• Programmable rising or falling edge strobe
• Power-down control function
• Compatible with TIA/EIA-644 LVDS standards
• Packaged in a 56-pin TSSOP (Pb free available)
Block Diagram
Red, Green, Blue 24
HSYNC
VSYNC
DATA ENABLE
CONTROL
R_FB
PWRDWN
CLOCK
TTL to
LVDS
PLL
TxOUT0+
TxOUT0-
TxOUT1+
TxOUT1-
TxOUT2+
TxOUT2-
TxOUT3+
TxOUT3-
TxCLKOUT+
TxCLKOUT-
V385A Datasheet
1
11/23/05
Revision 0.1
Integrated Circuit Systems • 525 Race Street, San Jose, CA 95126 • tel (408) 297-1201 • www.icst.com
Share Link: 