UPSD3253B-40 Просмотр технического описания (PDF) - STMicroelectronics

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UPSD3253B-40

Flash Programmable System Devices with 8032 Microcontroller Core and 256Kbit SRAM

STMicroelectronics 

µPSD325X DEVICES

Table 126. CPLD Macrocell Asynchronous Clock Mode Timing (3V Devices)

Symbol

Parameter

Conditions

Min

Max

PT

Aloc

Turbo Slew

Off Rate

Unit

Maximum Frequency

External Feedback

1/(tSA+tCOA)

21.7

MHz

fMAXA

Maximum Frequency

Internal Feedback (fCNTA)

1/(tSA+tCOA–10)

27.8

MHz

Maximum Frequency

Pipelined Data

1/(tCHA+tCLA)

33.3

MHz

tSA

Input Setup Time

10

+ 4 + 20

ns

tHA

Input Hold Time

12

ns

tCHA

Clock High Time

17

+ 20

ns

tCLA

Clock Low Time

13

+ 20

ns

tCOA

Clock to Output Delay

36

+ 20 – 6 ns

tARD

CPLD Array Delay

Any macrocell

25

+4

ns

tMINA

Minimum Clock Period

1/fCNTA

36

ns

161/176

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