UPD77112GC Просмотр технического описания (PDF) - NEC => Renesas Technology

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UPD77112GC

16-BIT FIXED-POINT DIGITAL SIGNAL PROCESSORS

NEC => Renesas Technology 

µPD77110, 77111, 77112

5.2.2 Host reboot

An instruction code is obtained via the host interface and transferred to the instruction RAM.

With the µPD77110, the host reboot mode is used to boot up the instruction RAM from addresses 0x4000 through

0xBFFF. Areas 0x0200 through 0x0FFF and 0x4000 through 0xBFFF cannot be rebooted all at once.

The entry address of the µPD77110 is 0x6, and that of the µPD77111 and 77112 is 0x5. Host reboot is executed

by calling this address after setting the following parameter:

• R7L : Number of instruction steps for rebooting

• DP3: First address of instruction memory to be loaded

5.3 Signature Operation

The µPD77110 has a signature operation function so that the contents of the internal instruction RAM can be

verified. The signature operation performs a specific arithmetic operation on the data in the instruction RAM booted

up, and returns the result to a register. Perform the signature operation in advance on the device when it is operating

normally, and repeat the signature operation later to check whether the data in RAM is correct by comparing the

operation result with the previous result. If the results are identical, there is no problem.

The entry address is 0x9. Execute the operation by calling this address after setting the following parameter.

Note that the operation cannot be performed on the areas 0x0200 through 0x0FFF and 0x4000 through 0xBFFF at

the same time. The operation result is stored in register R7.

• R7L: Number of instruction steps for operation

• DP3: First address of instruction memory for operation

6. STANDBY MODES

Two standby modes are available. By executing the corresponding instruction, each mode is set and the power

consumption can be reduced.

6.1 HALT Mode

To set this mode, execute the HALT instruction. In this mode, functions other than clock circuit and PLL are

stopped to reduce the current consumption.

To release the HALT mode, use an interrupt or hardware reset. When releasing the HALT mode using an

interrupt, the contents of the internal registers and memory are retained. It takes several 10 system clocks to release

the HALT mode when the HALT mode is released using an interrupt.

In the HALT Mode, the clock circuit of the µPD77111 family supplies the following clock as the internal system

clock. The clock output from the CLKOUT pin is as follows.

The clock output from the CLKOUT pin, however, has a high-level width that is equivalent to 1 cycle of the normal

operation (i.e., the duty factor is not 50%).

• µPD77110: 1/8 of internal system clock

• µPD77111, 77112: 1/l of internal system clock (l = integer from 1 to 16, specified by mask option)

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Data Sheet U12801EJ4V0DS00

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