UPD75236GJ Просмотр технического описания (PDF) - NEC => Renesas Technology
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UPD75236GJ Datasheet PDF : 190 Pages
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µPD75236
Table 2-4 µPD75236 I/O Map (3/5)
Address
Hardware Name (Symbol)
b3
b2
b1
b0
R/W No. of Manipulatable Bits Bit Manipulated
1 Bit 4 Bits 8 Bits Addressing
Remarks
FB0H
IST1 IST0 MBE RBE
q
R/W
Program status word (PSW)
—
FB2H
Interrupt priority select register (IPS) W
q
FB3H
Processor clock control register (PCC) W
q
FB4H
INT0 mode register (IM0)
W
—
FB5H
INT1 mode register (IM1)
W
—
FB7H
System clock control register (SCC) W
q
FB8H
IE4 IRQ4 IEBT IRQBT R/W
q
FB9H
EOT R/W
q
FBAH
IEW IRQW R/W
q
FBBH
IEKS IRQKS IETPG IRQTPG R/W
q
FBCH
IRQT1 IET0 IRQT0 R/W
q
FBDH
IECSI0 IRQCSI0 R/W
q
FBEH
IE1 IRQ1 IE0 IRQ0 R/W
q
FBFH
IE2 IRQ2 R/W
q
q
q
—
q
—
q
q
—
q
—
—
q
—
q
q
—
q
q
—
q
q
—
q
fmem.bit
5
Be sure to write 0 to bit 2.
Be sure to write 0 to bits 3, 2 and 1.
Only bits 3 and 0 are bit-manipulatable. 5
fmem.bit
FC0H
FC1H
Bit sequential buffer 0 (BSB0)
Bit sequential buffer 1 (BSB1)
R/W
q
R/W
q
q
q
q
FC2H
FC3H
Bit sequential buffer 2 (BSB2)
Bit sequential buffer 3 (BSB3)
R/W
q
R/W
q
q
q
q
FC8H
CSIM11 CSIM10 W
—
—
q
FC9H
CSIE1
W
q
—
5
FCCH
Serial I/O shift register (SI01)
R/W
—
—
q
25
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