UPD4704C Просмотр технического описания (PDF) - NEC => Renesas Technology

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UPD4704C

EXTENSION 8-BIT UP/DOWN COUNTER CMOS INTEGRATED CIRCUITS

NEC => Renesas Technology 

µPD4704

1. DESCRIPTION OF OPERATIONS

(1) Count operation

The µPD4704 is designed as 8-bit up/down counter for extension of the µPD4702. The first-stage Carry output

is connected to the UP input of the µPD4704, and similarly, the Borrow output is connected to the DOWN input. A

count is executed on the rising edge of the UP input or DOWN input.

If the µPD4704 is to be used alone, without being connected to the µPD4702, either UP or the DOWN must be "H".

If a count pulse is input to UP or DOWN while the other is "L", the count value may change.

(2) Latch operation

An R-S flip-flop is inserted in the latch circuit input as shown in Fig. 1, and when STB is changed from "H" to "L"

while the UP or DOWN input is "L", the internal latch signal STB' remains at "H" until the end of the count operation.

Therefore, latching is not performed during a count operation. If STB changes from "H" to "L" tSUDSTB1 (40 ns) or

more after the falling edge of UP or DOWN, the post-count data is latched, and if STB changes from "H" to "L" within

tSUDSTB2 (10 ns) after the falling edge of UP or DOWN, then conversely, the pre-count data is latched.

Caution is required since, when UP or DOWN is "L" (during a count operation), the latch operation is kept waiting

even if STB is changed from "H" to "L", and therefore if a reset is executed the latch contents will also be reset (see

Figs. 2 and 3).

Fig. 1 STB Input Circuit

From UP/DOWN Circuit

Count Clock

STB'

STB

4

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