UPD3739 Просмотр технического описания (PDF) - NEC => Renesas Technology
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UPD3739 Datasheet PDF : 24 Pages
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µPD3739
ABSOLUTE MAXIMUM RATINGS (TA = +25 ˚C)
Parameter
Output drain voltage
Shift register clock voltage
Reset gate clock voltage
Transfer gate clock voltage
Operating ambient temperature
Storage temperature
Symbol
Ratings
Unit
VOD
–0.3 to +15
V
Vφ1, Vφ2
–0.3 to +15
V
VφR1, VφR2
–0.3 to +15
V
VφTG
–0.3 to +15
V
TA
–25 to +55
˚C
Tstg
–40 to +100
˚C
Caution Exposure to ABSOLUTE MAXIMUM RATINGS for extended periods may affect device reliability;
exceeding the ratings could cause permanent damage. The parameters apply independently.
RECOMMENDED OPERATING CONDITIONS (TA = –25 to +55 ˚C)
Parameter
Output drain voltage
Shift register clock high level
Shift register clock low level
Reset gate clock high level
Reset gate clock low level
Capacitance of reset gate clock pin external capacitor
Transfer gate clock high level
Transfer gate clock low level
Data rate
Symbol
Conditions
VOD
Vφ1H, Vφ2H
Vφ1L, Vφ2L
VφR1H, VφR2H Note
VφR1L, VφR2L Note
CEXTφR
Non-polar type
VφTGH
VφTGL
2fφR1, 2fφR2
MIN.
11.4
4.5
–0.3
4.5
–0.3
800
4.5
–0.3
0.5
TYP.
12.0
5.0
0
5.0
0
1000
5.0
0
2
MAX.
12.6
5.5
+0.5
5.5
+0.5
1200
5.5
+0.5
40
Unit
V
V
V
V
V
pF
V
V
MHz
Note Input the reset gate clocks 1 and 2 (φR1, φR2) to pins 5 and 18, respectively, via an input resistor and a capacitor.
Use of a capacitor is indispensable. Refer to APPLICATION CIRCUIT EXAMPLE for the connection method.
The reset gate clock high level and low level at the IC pins (after passing through the external capacitor) varies
according to the IC, due to the on-chip automatic φR level adjuster. The recommended operating conditions
of reset gate clocks 1, 2 (φR1, φR2) in the table above are for signals applied to the external capacitor.
Remark φ1 in the above tables represents φ11, φ12 and φ1L2. φ2 represents φ21, φ22 and φ2L1.
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