UPD16337W Просмотр технического описания (PDF) - NEC => Renesas Technology
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UPD16337W Datasheet PDF : 16 Pages
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PIN CONFIGURATION (Top View)
µPD16337
NC
VDD2
NC
VSS2
NC
O43
O44
O45
O46
O47
O48
O49
O50
O51
O52
O53
O54
O55
O56
O57
O58
O59
O60
O61
O62
O63
O64
NC
VDD2
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
10
71
11
70
12
69
13
68
14
67
15
66
16
100-pin plaxtic QFP
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
VDD2
NC
VSS2
NC
O22
O21
O20
O19
O18
O17
O16
O15
O14
O13
O12
O11
O10
O9
O8
O7
O6
O5
O4
O3
O2
O1
NC
VDD2
NC
Cautions 1. Pin 40 is connected to the lead frame, and therefore must be left open.
2. Ensure that the VDD1, VDD2, VSS1 and VSS2 pins are all used, and that VSS1 and VSS2 are used
at the same potential.
3. To prevent latch up breakdown, the power should be turned on in the order VDD1, logic signal,
VDD2. It should be turned off in the opposite order.
3
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