UDA1384H Просмотр технического описания (PDF) - Philips Electronics

Номер в каталоге

Компоненты Описание

производитель

UDA1384H

Multichannel audio coder-decoder

Philips Electronics 

Philips Semiconductors

UDA1384

Multichannel audio coder-decoder

8.2 Audio analog-to-digital converter (audio ADC)

The audio analog-to-digital front-end of the UDA1384 consists of 4-channel single-ended

ADCs with programmable gain stage (from 0 dB to 24 dB with 3 dB steps), controlled via

the microcontroller interface. Using the PGA feature, it is possible to accept an input signal

of 900 mV (RMS) or 1.8 V (RMS) if an external resistor of 10 kΩ is used in series. The

schematic of audio ADC front-end is shown in Figure 3.

input signal

2 V (RMS)

VINL,

10 kΩ VINR

10 kΩ (0 dB setting)

10 kΩ

ADC

Vref

VDDA = 3.3 V

mgu582

Fig 3. Schematic of audio ADC front-end

8.3 Voice Analog-to-Digital Converter (voice ADC)

The voice analog-to-digital front-end of the UDA1384 consists of a single-channel

single-ended ADC with a fixed gain (26 dB) Low Noise Amplifier (LNA). Together with the

digital variable gain amplification stage, the voice ADC provides optimal processing and

reproduction of the microphone signal. The supported sampling frequency range is from

7 kHz to 50 kHz. Power-down of the LNA and the ADC can be controlled separately.

8.4 Decimation filter of audio ADC

The

decimation

from

64fs

is

performed

in

two

stages.

The

first

stage

realizes





-s--i--xn----x-

4

characteristics with a decimation factor of 8. The second stage consists of three half-band

filters, each decimating by a factor of 2. The filter characteristics are shown in Table 7.

Table 7: Decimation filter characteristics (audio ADC)

Item

Condition

Pass-band ripple

0fs to 0.45fs

Pass-band droop

0.45fs

Stop band

> 0.55fs

Dynamic range

0fs to 0.45fs

Value (dB)

±0.01

−0.2

−70

> 135

8.5 Decimation filter of voice ADC

The voice ADC decimation filter is realized with the combination of a Finite Impulse

Response (FIR) filter and Infinite Impulse Response (IIR) filter for shorter group delay. The

filter characteristics are shown in Table 8. During the power-on sequence, the output of

the ADC is hard muted for a certain period. This hard-mute time can be chosen between

1024 samples and 2048 samples.

9397 750 14366

Product data sheet

Rev. 02 — 17 January 2005

© Koninklijke Philips Electronics N.V. 2005. All rights reserved.

8 of 55

Share Link: