UDA1351 Просмотр технического описания (PDF) - Philips Electronics

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UDA1351

96 kHz IEC 958 audio DAC

Philips Electronics 

Philips Semiconductors

96 kHz IEC 958 audio DAC

Preliminary specification

UDA1351H

8.2 Clock regeneration and lock detection

The UDA1351H contains an on-board PLL for

regenerating a system clock from the IEC 958 input

bitstream or the incoming digital data stream via the data

input interface. In addition to the system clock for the

on-board digital sound processing the PLL also generates

a 256fs clock output for use in the application. In the

absence of an input signal the clock will generate a

minimum frequency to warrant system functionality.

Note: in case of no input signal, the PLL generates a

minimum frequency and the output spectrum shifts

accordingly. Since the analog output does not have a

analog mute, this means noise which is out of band noise

under normal operation conditions, can move into the

audio band.

When the on-board clock has locked to the incoming

frequency the lock indicator bit will be set and can be read

via the L3 interface. Internally the PLL lock indication is

combined with the PCM status bit of the input data stream.

When both the IEC 958 decoder and the on-board clock

have locked to the incoming signal and the input data

stream is PCM data, then pin LOCK will be asserted.

However, when the IC is locked but the PCM status bit

reports non-PCM data then pin LOCK is returned to LOW

level.

The lock indication output can be used, for example, for

muting purposes. The lock signal can be used to drive an

external analog muting circuit to prevent out of band noise

to become audible in case the PLL runs at its minimum

frequency (e.g. when there is no SPDIF input signal).

8.3 Mute

The UDA1351H is equipped with a cosine roll-off mute in

the DSP data path of the DAC part. Muting the DAC, by

pin MUTE (in static mode) or via bit MT (in L3 mode) will

result in a soft mute as presented in Fig.3. The cosine

roll-off soft mute takes 32 × 32 samples = 24 ms at a

sampling frequency of 44.1 kHz.

handbook, h1alfpage

mute

factor

0.8

MGS755

0.6

0.4

0.2

0

0

1

2 t (ms) 3

Fig.3 Mute as a function of raised cosine roll-off.

When operating in the L3 control mode the device will

mute on start-up. In L3 mode it is necessary to explicitly

switch off the mute for audio output by means of the MT bit

in the L3 register.

In the L3 mode pin MUTE does not have any function (the

same holds for several other pins) and can either be left

open-circuit (since it has an internal pull-down resistor) or

be connected to ground.

2000 Feb 18

10

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