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UDA1340M

Low-voltage low-power stereo audio CODEC with DSP features

Philips Electronics 

Philips Semiconductors

Low-voltage low-power stereo audio

CODEC with DSP features

Preliminary specification

UDA1340

L3-Interface

The UDA1340 has a microcontroller input mode. In the

microcontroller mode, all the digital sound processing

features and the system controlling features can be

controlled by the microcontroller. The controllable features

are:

• System clock frequency

• Data input format

• Power control

• DC-filtering

• De-emphasis

• Volume

• Flat/min/max switch

• Bass boost

• Treble

• Mute.

The exchange of data and control information between the

microcontroller and the UDA1340 is accomplished through

a serial hardware interface comprising the following pins:

L3DATA: microcontroller interface data line

L3MODE: microcontroller interface mode line

L3CLOCK: microcontroller interface clock line.

Information transfer via the microcontroller bus is

organized in accordance with the so called ‘L3’ format, in

which two different modes of operation can be

distinguished; address mode and data transfer mode

(see Figs 4 and 5).

The address mode is required to select a device

communicating via the L3-bus and to define the

destination registers for the data transfer mode. Data

transfer for the UDA1340 can only be in one direction,

input to the UDA1340 to program its sound processing and

other functional features.

Address mode

The address mode is used to select a device for

subsequent data transfer and to define the destination

registers. The address mode is characterized by L3MODE

being LOW and a burst of 8 pulses on L3CLOCK,

accompanied by 8 data bits. The fundamental timing is

shown in Fig.4. Data bits 0 to 1 indicate the type of

subsequent data transfer as given in Table 4.

Table 4 Selection of data transfer

BIT 1

0

0

1

1

BIT 0

TRANSFER

0 DATA (volume, bass boost, treble,

de-emphasis, mute, mode and power

control)

1 not used

0 STATUS (system clock frequency, data

input format and DC-filter)

1 not used

Data bits 7 to 2 represent a 6-bit device address, with bit 7

being the MSB and bit 2 the LSB. The address of the

UDA1340 is 000101 (bit 7 to bit 2). In the event that the

UDA1340 receives a different address, it will deselect its

microcontroller interface logic.

Data transfer mode

The selection preformed in the address mode remains

active during subsequent data transfers, until the

UDA1340 receives a new address command.

The fundamental timing of data transfers is essentially the

same as in the address mode, shown in Fig.4.

The maximum input clock and data rate is 64fs.

All transfers are byte wise, i.e. they are based on groups

of 8 bits. Data will be stored in the UDA1340 after the

eighth bit of a byte has been received. A multibyte transfer

is illustrated in Fig.6.

PROGRAMMING THE SOUND PROCESSING AND OTHER

FEATURES

The sound processing and other feature values are stored

in independent registers. The first selection of the registers

is achieved by the choice of data type that is transferred.

This is performed in the address mode, BIT 1 and BIT 0

(see Table 4). The second selection is performed by the

2 MSBs of the data byte (BIT 7 and BIT 6). The other bits

in the data byte (BIT 5 to BIT 0) is the value that is placed

in the selected registers.

When the data transfer of type ‘data’ is selected, the

features VOLUME, BASS BOOST, TREBLE,

DE-EMPHASIS, MUTE, MODE and POWER CONTROL

can be controlled. When the data transfer of type ‘status’

is selected, the features SYSTEM CLOCK FREQUENCY,

DATA INPUT FORMAT and DC-FILTER can be

controlled.

1997 Jul 09

9

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