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UDA1340

Low-voltage low-power stereo audio CODEC with DSP features

Philips Electronics 

Philips Semiconductors

Low-voltage low-power stereo audio

CODEC with DSP features

Preliminary specification

UDA1340

FUNCTIONAL DESCRIPTION

System clock

The UDA1340 accommodates slave mode only, this

means that in all applications the system devices must

provide the system clock. The system frequency is

selectable. The options are 256fs, 384fs and 512fs.

The system clock must be locked in frequency to the digital

interface input signals.

Multiple format input/output interface

The UDA1340 supports the following data input/output

formats:

• I2S-bus with data word length of up to 20 bits

• MSB justified serial format with data word length of up to

20 bits

• LSB justified serial format with data word lengths of

16, 18 or 20 bits.

The formats are illustrated in Fig.3. Left and right

data-channel words are time multiplexed.

Analog-to-Digital Converter (ADC)

The stereo ADC of the UDA1340 consists of two

third-order Sigma-Delta modulators. They have a modified

Ritchie-coder architecture in a differential switched

capacitor implementation. The over-sampling ratio is 128.

Decimation filter (ADC)

The decimation from 128fs is performed in two stages.

The first stage realizes 3rd-order s----i-nx-----x- characteristic. This

filter decreases the sample rate by 16. The second stage,

an FIR filter, consists of 3 half-band filters, each

decimating by a factor of 2.

Table 1 Decimation filter characteristics

ITEM

Passband Ripple

Stop band

Dynamic range

Gain

CONDITION

0 − 0.45fs

>0.55fs

0 − 0.45fs

overall

VALUE (dB)

±0.05

−60

108

−1.16

DC cancellation filter (ADC)

An optional IIR high-pass filter is provided to remove

unwanted DC components. The operation is selected by

the microcontroller via the L3-bus. The filter characteristics

are given in Table 2.

Table 2 DC cancellation filter characteristics

ITEM

Passband ripple

Passband gain

Droop

Attenuation at DC

Dynamic range

CONDITION

at 0.00045fs

at 0.00000036fs

0 − 0.45fs

VALUE (dB)

none

0

0.031

>40

>110

Mute (ADC)

On recovery from power-down or switching on of the

system clock, the serial data output DATAO is held LOW

until valid data is available from the decimation filter. This

time depends on whether the DC cancellation filter is

selected:

DC cancel off: time = 1----0-f--s2----4- , t = 23.2 ms when

fs = 44.1 kHz

DC cancel on: time = 1----2---f2--s--8---8-- , t = 279 ms when

fs = 44.1 kHz

Overload detection (ADC)

In practice the output is used to indicate whenever the

output data, in either the left or right channel, is greater

than −1 dB (actual figure is −1.16 dB) of the maximum

possible digital swing. When this condition is detected the

OVERFL output is forced HIGH for at least 512fs cycles

(11.6 ms at fs = 44.1 kHz). This time-out is reset for each

infringement.

1997 Jul 09

6

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