TZA3044T Просмотр технического описания (PDF) - Philips Electronics
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производитель
TZA3044T Datasheet PDF : 28 Pages
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Philips Semiconductors
SDH/SONET STM4/OC12 and
1.25 Gbits/s Gigabit Ethernet postamplifiers
Product specification
TZA3044; TZA3044B
PINNING
PIN
SYMBOL TZA3044T
TZA3044TT
PAD
TZA3044U
TYPE(1)
DESCRIPTION
SUB
TEST
1
1, 14
S substrate pin; must be at the same potential as pin AGND
2
2, 10, 15,
− for test purpose only; to be left open in the application
21, 26
AGND
3
3, 4, 6, 9
S analog ground; must be at the same potential as pin DGND
DIN
4
7
I differential input; complementary to pin DINQ; DC bias level is set
internally at approximately 2.1 V
DINQ
5
8
I differential input; complementary to pin DIN; DC bias level is set
internally at approximately 2.1 V
VCCA
CF
JAM
6
11, 12
S analog supply voltage; must be at the same potential as pin VCCD
7
13
A input for connection of capacitor to set time constant of level
detector input filter (optional); the capacitor should be connected
between VCCA and pin CF
8
16
I PECL-compatible input (TTL compatible for the TZA3044B);
controls the output buffers pins DOUT and DOUTQ; when a LOW
signal is applied, the outputs will follow the input signal; when a
HIGH signal is applied, the output buffers will latch into LOW and
HIGH states respectively; when not connected, pin JAM is actively
pulled LOW
STQ
9
17
O PECL-compatible status output of the input signal level detector
(TTL compatible for the TZA3044B); when the input signal is below
the user-programmed threshold level, this output is HIGH;
complementary to pin ST
ST
10
18
O PECL-compatible status output of the input signal level detector
(TTL compatible for the TZA3044B); when the input signal is below
the user-programmed threshold level, this output is LOW;
complementary to pin STQ
DGND
11
19, 20, 22, S digital ground; must be at the same potential as pin AGND
25
DOUTQ
12
23
O PECL-compatible differential output; forced into a HIGH condition
when pin JAM is HIGH; complementary to pin DOUT
DOUT
13
24
O PECL-compatible differential output; forced into a LOW condition
when pin JAM is HIGH; complementary to pin DOUTQ
VCCD
Vref
RSET
n.c.
14
27, 28
S digital supply voltage; must be at the same potential as VCCA
15
29
O band gap reference voltage; typical value is 1.2 V; internal series
resistor of 1 kΩ
16
30
A input signal level detector programming; nominal DC voltage is
VCCA − 1.5 V; threshold level is set by connecting an external
resistor between VCCA and pin RSET or by forcing a current into
pin RSET; default value for this resistor is 180 kΩ which
corresponds with approximately 4 mV (p-p) differential input signal
−
5, 31, 32
− not connected
Note
1. Pin type abbreviations: O = Output, I = Input, S = power Supply and A = Analog function.
1999 Nov 03
4
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