TZA3044U Просмотр технического описания (PDF) - Philips Electronics
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TZA3044U Datasheet PDF : 28 Pages
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Philips Semiconductors
SDH/SONET STM4/OC12 and
1.25 Gbits/s Gigabit Ethernet postamplifiers
Product specification
TZA3044; TZA3044B
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX. UNIT
PECL output pins ST and STQ (TZA3044)
VOL
LOW-level output voltage
note 8
VOH
HIGH-level output voltage note 8
CL
load capacitance
RL = ∞
RL = 1 kΩ
RL = 50 Ω
VCC − 1.84 −
VCC − 1.1 −
−
−
−
−
−
−
VCC − 1.6 V
VCC − 0.9 V
20
pF
100
pF
1000
pF
TTL output pins ST and STQ (TZA3044B)
VOL
LOW-level output voltage
IOL = 4 mA
VOH
HIGH-level output voltage IOH = −400 µA
−
−
2.4
−
0.4
V
−
V
PECL input pin JAM (TZA3044)
VIL
VIH
II(JAM)
LOW-level input voltage
HIGH-level input voltage
JAM input current
note 10
−
−
VCC − 1.165 −
−20
−
VCC − 1.49 V
−
V
+20
µA
TTL input pin JAM (TZA3044B)
VIL
VIH
II(JAM)
LOW-level input voltage
HIGH-level input voltage
JAM input current
note 10
−
−
2.0
−
−20
−
0.8
V
−
V
+20
µA
Reference voltage output pin Vref
Vref
reference voltage
note 11
1.165
1.20
1.235
V
Notes
1. PECL outputs (pins DOUT, DOUTQ, ST and STQ) are not connected.
2. Maximum currents are specified at Tj = 125 °C, VCC = 5.5 V and worst case processing.
3. 2 mV (p-p) single-ended is the minimum input signal to achieve full clipping of the output signal. Typical an input
signal of 0.8 mV (p-p) single-ended results in a Bit Error Rate (BER) of less than 10−10.
4. If the input is DC coupled, the preceding amplifier’s output offset voltage should not exceed these limits, in order to
avoid malfunctioning of the DC offset compensation circuit.
5. Specifications guaranteed by design and characterisation. Each device is tested at full operating speed to guarantee
RF functionality.
6. Input RMS noise = t--o----tl-ao----lw---o---fu-r--et--p--q-u--u--t-e--R--n--M-c---y-S----g--n-a--o-i--n-i-s---e--
7. The reference current can be set by connecting a resistor between VCCA and pin RSET. The corresponding input
signal level detect range is from 2 to 12 mV (p-p) single-ended. See Section “Input signal level detection” for detailed
information.
8. RL = 50 Ω connected to a level of VCC − 2 V (see Fig.9).
9. Large signal response of TZA3044T and TZA3044TT show very little deviation, although the small signal frequency
response of the TZA3044TT is more flat and shows a larger bandwidth.
10. Internal pull-down resistor of 500 kΩ to DGND.
11. Internal series resistor of 1 kΩ.
1999 Nov 03
12
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