TZA3044(1998) Просмотр технического описания (PDF) - Philips Electronics

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производитель

TZA3044
(Rev.:1998)

1.25 Gbits/s Gigabit Ethernet postamplifiers

Philips Electronics 

Philips Semiconductors

1.25 Gbits/s Gigabit Ethernet postamplifiers

Objective specification

TZA3044T; TZA3044U

more than a few millivolt should be avoided, since the

internal DC offset compensation circuit has a limited

correction range.

If AC coupling is used to remove any DC compatibility

requirement, the coupling capacitors must be large

enough to pass the lowest input frequency of interest.

For example, 1 nF coupling capacitors react with the

internal 4.5 kΩ input bias resistors to yield a lower −3 dB

frequency of 35 kHz. This then sets a limit on the

maximum number of consecutive pulses that can be

sensed accurately at the system data rate. Capacitor

tolerance and resistor variation must be included for an

accurate calculation.

DC-offset compensation

A control loop connected between the inputs of buffer A3

and amplifier A1 (see Fig.1) will keep the input of buffer A3

at its toggle point in the absence of any input signal.

Because of the active offset compensation which is

integrated in the TZA3044, no external capacitor is

required. The loop time constant determines the lower

cut-off frequency of the amplifier chain, which is set at

approximately 850 Hz.

Input signal level-detection

The TZA3044 allows for user-programmable input signal

level-detection and can automatically disable the switching

of the PECL outputs if the input signal is below a set

threshold. This prevents the outputs from reacting to noise

in the absence of a valid input signal, and insures that data

will only be transmitted when the signal-to-noise ratio of

the input signal is sufficient for low bit-error-rate system

operation. Complementary PECL flags (ST and STQ)

indicate whether the input signal is above or below the

programmed threshold level.

The input signal is amplified and rectified before being

compared to a programmable threshold reference. A filter

is included to prevent noise spikes from triggering the

level-detector. This filter has a nominal 1 µs time constant

and additional filtering can be achieved by using an

external capacitor between pin CF and VCCA (the internal

driving impedance nominally is 25 kΩ). The resultant

signal is then compared to a threshold current through

pin RSET (see Fig.6). This current can be set by

connecting an external resistor RDETECT between

pin RSET and VCCA, or by forcing a current into pin RSET.

The relationship between the threshold current and the

detected input voltage is approximately:

IRSET = 0.002 × ( VDIN – VDINQ) [ A]

(1)

Since the voltage on pin RSET is held constant at 1.5 V

below VCCA, the current flowing into this pin will be:

IRSET = R-----D----1E---.T--5-E----C---T- [ A]

(2)

Combining these two formulas results in a general formula

to calculate RDETECT for a given input signal

level-detection:

RDETECT = --(--V----D----I--N---7-–--5---V0----D----I-N----Q----)- [ Ω]

(3)

In this formula, VDIN and VDINQ are in V (p-p).

Example: Detection should occur if the differential voltage

of the input signals drops below 4 mV (p-p). In this case, a

reference current of 0.002 × 0.004 = 8 µA should flow into

pin RSET. This can be set using a current source or simply

by connecting a resistor of the appropriate value.

The resistor must be connected between VCCA and

pin RSET. In this example the resistor would be:

RDETECT = 0----.7--0-5--0--0--4--- = 187.5 kΩ

The hysteresis is fixed internally at 3 dB electrical. In the

example of above, a differential level below 4 mV (p-p) of

the input signal will drive pin ST to LOW, and an input

signal level above 5.7 mV (p-p) will drive pin ST to HIGH.

Since a JAM function is provided which forces the data

outputs to a predetermined state (DOUT = LOW and

DOUTQ = HIGH), the pins STQ and JAM can be

connected to automatically disable the signal transmission

when the chip senses that the input signal is below the

programmed threshold.

Response time of the input signal level-detection circuit is

determined by the time constant of the input capacitors,

together with the filter time constant (1 µs internal plus the

additional capacitor at pin CF).

PECL output circuits

The output circuit of ST and STQ is given in Fig.7

The output circuit of DOUT and DOUTQ is given in Fig.8.

Some PECL termination schemes are given in Fig.9.

1998 Jul 07

6

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