TZA3044(1998) Просмотр технического описания (PDF) - Philips Electronics
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производитель
TZA3044 Datasheet PDF : 18 Pages
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Philips Semiconductors
1.25 Gbits/s Gigabit Ethernet postamplifiers
Objective specification
TZA3044T; TZA3044U
PINNING
SYMBOL PIN
TYPE
DESCRIPTION
SUB
1 substrate
substrate pin; must be at the same potential as AGND (pin 3)
TEST
2 test pin
for test purpose only; to be left open in the application
AGND
3 ground
analog ground; must be at the same potential as DGND (pin 11)
DIN
4 analog input differential input; DC bias level is set internally at approximately 2.55 V;
complimentary to DINQ (pin 5)
DINQ
5 analog input differential input; DC bias level is set internally at approximately 2.55 V;
complimentary to DIN (pin 4)
VCCA
CF
JAM
6 supply
analog supply voltage; must be at the same potential as VCCD (pin 14)
7 analog input filter capacitor for input signal level detector; capacitor should be connected
between this pin and VCCA (pin 6)
8 PECL input PECL-compatible input; controls the output buffers DOUT and DOUTQ
(pins 13 and 12). When a LOW signal is applied, the outputs will follow the input
signal. When a HIGH signal is applied, the DOUT and DOUTQ pins will latch into
LOW and HIGH states, respectively. When left unconnected, this pin is actively
pulled LOW (JAM OFF).
STQ
9 PECL output PECL-compatible status output of the input signal level detector; when the input
signal is below the user-programmed threshold level, this output is HIGH;
complimentary to ST (pin 10)
ST
10 PECL output PECL-compatible status output of the input signal level detector; when the input
signal is below the user-programmed threshold level, this output is LOW;
complimentary to STQ (pin 9)
DGND
11 ground
digital ground; must be at the same potential as AGND (pin 3)
DOUTQ
12 PECL output PECL-compatible differential output; when JAM is HIGH, this pin will be forced
into a HIGH condition; complimentary to DOUT (pin 13)
DOUT
13 PECL output PECL-compatible differential output; when JAM is HIGH, this pin will be forced
into a LOW condition; complimentary to DOUTQ (pin 12)
VCCD
Vref
RSET
14 supply
digital supply voltage; must be at the same potential as VCCA (pin 6)
15 analog output band gap reference voltage; typical value is 1.2 V; internal series resistor of 1 kΩ
16 analog input input signal level detector programming; nominal DC voltage is VCCA − 1.5 V;
threshold level is set by connecting an external resistor between RSET and VCCA
or by forcing a current into RSET; default value for this resistor is 180 kΩ which
corresponds with approximately 4 mV (p-p) differential input signal
1998 Jul 07
3
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