5962-0324601Q9A Просмотр технического описания (PDF) - Atmel Corporation
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5962-0324601Q9A Datasheet PDF : 42 Pages
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Wait-state and Time-out
Generator
TSC695FL
Table 2. System Registers Address Map (Continued)
System Register Name
Memory Configuration Register
MCNFR
I/O Configuration Register
IOCNFR
Waitstate Configuration Register
WSCNFR
Access Protection Segment 1 Base Register
APS1BR
Access Protection Segment 1 End Register
APS1ER
Access Protection Segment 2 Base Register
APS2BR
Access Protection Segment 2 End Register
APS2ER
Interrupt Shape Register
INTSHR
Interrupt Pending Register
INTPDR
Interrupt Mask Register
INTMKR
Interrupt Clear Register
INTCLR
Interrupt Force Register
INTFCR
Watchdog Timer Register
WDOGTR
Watchdog Timer Trap Door Set
WDOGST
Real Time Clock Timer <Counter> Register
RTCCR
Real Time Clock Timer <Scaler> Register
RTCSR
General Purpose Timer <Counter> Register
GPTCR
General Purpose Timer <Scaler> Register
GPTSR
Timers Control Register
TIMCTR
General Purpose Interface Configuration Register
GPICNFR
General Purpose Interface Data Register
GPIDATR
UART ’A’ Rx & Tx Register
UARTAR
UART ’B’ Rx & Tx Register
UARTBR
UART Status Register
UARTSR
Address
0x 01F8 0010
0x 01F8 0014
0x 01F8 0018
0x 01F8 0020
0x 01F8 0024
0x 01F8 0028
0x 01F8 002C
0x 01F8 0044
0x 01F8 0048
0x 01F8 004C
0x 01F8 0050
0x 01F8 0054
0x 01F8 0060
0x 01F8 0064
0x 01F8 0080
0x 01F8 0084
0x 01F8 0088
0x 01F8 008C
0x 01F8 0098
0x 01F8 00A8
0x 01F8 00AC
0x 01F8 00E0
0x 01F8 00E4
0x 01F8 00E8
It is possible to control the wait state generation by programming a Waitstate Configura-
tion Register. The maximum programmable number of wait-states is applied by default
at reset.
It is possible to program the number of wait states for the following combinations:
– RAM read and write
– PROM read and write (i.e. EEPROM or Flash write)
– Exchange Memory read/write
– Four individual I/O peripherals read/write
7
4204C–AERO–05/05
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