TQ9502MC Просмотр технического описания (PDF) - TriQuint Semiconductor

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TQ9502MC

531/1063 Mbaud Fibre Channel Transmitter and Receiver

TriQuint Semiconductor 

TQ9501/TQ9502

Layout Guidelines

Multiple ground and power pins on the TQ9501/02

reduce ground bounce. Good layout techniques,

however, are necessary to guarantee proper operation

and to meet the specifications across the full operating

range. TriQuint recommends bypassing each of the VDD

supply pins to the nearest ground pin, as close to the

chip as possible.

Figure 7 shows the recommended power layout for the

TQ9501/02. The bypass capacitors should be located

on the same side of the board as the TQ9501/02. The

VDD traces connect to an inner-layer VDD plane. All of

the ground pins (GND) are connected to a small ground

plane on the surface beneath the chip. Multiple

through-holes connect this small surface plane to an

inner-layer ground plane. The capacitors are 0.1 µF.

TriQuint's test board uses X7R temperature-stable

capacitors in 1206 SMD cases.

Figure 7. Example Top Layer Layout of Power Pins

(Not to scale)

VDD

C

Pin 1

Ground

Plane

Rx Only

VDD

VDD

C

Pin 23

C

VDD

VDD

C

C

VDD

VDD

C

Note: Series resistors and small capacitors may be needed for the

TX data bus and clock lines. See the previous “Fibre Channel

Interface” section in this datasheet for details.

Table 4. Absolute Maximum Ratings

Table 5. Operating Conditions

Parameter

Storage temperature

Case temperature

Supply voltage to ground

DC input voltage

DC input current

Package Thermal Resistance

Die Junction Temperature

Range

–65 °C to +150 °C

–55 °C to +125 °C

–0.5 V to +7.0 V

–0.5 V to (VDD +0.5 V)

30 mA to +5 mA

θjA = 40 °C/W; θcA = 8 °C/W

Tj = 150 °C

Parameter

Supply voltage

Ambient temperature

Range

5V±5

0 to 70 °C

Note: Proper functionality is guaranteed under these

operating conditions.

Note:

Stresses above those listed in Absolute Maximum Rating

may cause permanent damage to the device. This is a

stress-only rating and operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied.

Table 6. Test Loads

Symbol

CIN

COUT

Description

Input capacitance

Output capacitance

Test Conditions

VIN = 2.0 V at f = 1 MHz

VOUT = 2.0 V at f = 1 MHz

Min.

Typ.

Max.

Unit

6

pF

9

pF

8

For additional information and latest specifications, see our website: www.triquint.com

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