TQ9501 Просмотр технического описания (PDF) - TriQuint Semiconductor
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TQ9501 Datasheet PDF : 16 Pages
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TQ9501/TQ9502
Table 3. Receiver Pin Descriptions
Symbol
RX, RY
RTX, RTY
RLX, RLY
RLTX, RLTY
LOOPEN
REFCLK
SYNCEN
RXDO..9
SYNC
RXCLK
CLKPOL
RATESEL
Type
I
I
I
I
I
I
I
O
O
O
O
I
Description
The Receiver Differential Inputs connects to an optical, coaxial or shielded twisted pair interface.
LOOPEN low selects the RX and RY inputs. LOOPEN high selects the RLX and RLY inputs.
The Receiver Differential Termination are used in Fly-By™ termination. RX is internally connected to
RTX and RY is internally connected to RTY. A termination circuit connects to RTX and RTY instead of
RX and RY. With Fly-By™ termination, the termination circuit can be located away from the Receiver
instead of requiring termination directly at RX and RY. Both RTX and RTY must be terminated with a
50Ω chip resistor in series with 3V reference or Thevenin equivalent as shown in Figure 6.
The Looped Receiver Differential Inputs connect to the Transmitters TLX and TLY outputs providing
a loop back path. LOOPEN high selects the RLX and RLY inputs. LOOPEN low selects the RX and RY
inputs.
The Receiver Differential Termination are used in Fly-By™ termination. RLX is internally connected
to RLTX and RLY is internally connected to RLTY. A termination circuit connects to RLTX and RLTY
instead of RLX and RLY. With Fly-BY™ termination, the termination circuit can be located away from
the Receiver instead of requiring termination directly at the RLX and RLY. Both RLTX and RLTY must
be terminated with a 50Ω chip resistor in series with 3V reference or Thevenin equivalent as shown
on Figure 6.
Loopback Enable high selects the RLX and RLY inputs. LOOPEN low selects the RX and RY inputs.
The Reference Clock provides the clock needed by the clock recovery circuit. The REFCLK frequency
shall bE chosen to equal 1/40 of the baud rate. REFCLK shall have a frequency tolerance of 100 ppm
to guarantee clock and data recovery on the receiver. The receiver automatically locks onto the
REFCLK during power-up and/or when no input signals are applied. This prevents the PLL from
drifting away from the input data rate. The PLL automatically locks onto the input data stream when it
is applied. The frequency range of REFCLK is 25 MHz to 31.25 MHz.
When Sync Enable is high, the receiver searches for a K28.5 character from the input data stream and
byte aligns the parallel register to this character as defined in the Fibre Channel standard. SYNCEN
low disables byte alignment to a K28.5 character and drives SYNC low. The K28.5 character has a
pattern of RXD9..0 = 001111 1010 or 110000 0101. Whenever the receiver detects the K28.5 pattern
it byte aligns to this character and drives SYNC high for that byte cycle. SYNC is high only in byte
cycle where a K28.5 character is present.
These are 10 Encoded Data Bits where the first bit received from the serial data stream is RXD9 and
the last bit received is RXD0. The receiver generates RXCLK to strobe RXD0..9.
If SYNCEN is high, Synchronization to K28.5 goes high for the byte clock cycle in which a K28.5
character is present on the RXD0..9 output. If SYNCEN is low then SYNC is always low.
Receiver Data Clock is the strobe for RXD0..9 and SYNC. The phase of RXCLK with respect to
RXD0..9 and SYNC changes depending on CLKPOL. CLKPOL high provides a longer setup time and a
shorter hold time while CLKPOL low provides a shorter setup time and a longer hold time. The
frequency range of RXCLK is 50 MHz to 62.5 MHz in FC531 mode and 100 MHz to 125 MHz in FC1063
mode.
Clock Phase or Polarity controls the phase of RXCLK with respect to RXD0..9 and SYNC. CLKPOL
high provides a longer setup time and a shorter hold time while CLKPOL low provides a shorter setup
time and a longer hold time.
Rate Select is used to select between 531 Mbaud (RATESEL=VDD) and 1063 Mbaud
(RATESEL=GND) operation.
For additional information and latest specifications, see our website: www.triquint.com
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