TQ9502MC Просмотр технического описания (PDF) - TriQuint Semiconductor

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производитель

TQ9502MC

531/1063 Mbaud Fibre Channel Transmitter and Receiver

TriQuint Semiconductor 

TQ9501/TQ9502

Figure 3. System Block Diagram – Fibre Channel

Host

RATESEL

REFCLK

LOOPEN

TQ9501 TX

SIGDET

TQ9303 ENDEC

CTXD0..31 BTXD0..9

CTXC0,1 BTXCKOUT

CTXP0..3 BTXCKIN

CTXRAWA,B

CTXRAW

CTXPENN

CTXPMODE

CTXPERR

CTXCERR

CTXCLK

CTXWREF

TX, TY

TXD0..9 TLX, TLY

TXCLK

BYTECLK

RATESEL

REFCLK

LOOPEN

SIG, SIGN

RESETN

CRXD0..31

CRXP0..3

CRXS0..5

RAWRX

RXPMODE

BRXD0..9

BRXCLK

BRXSYNC

WRDSYNCN

RXCKPH0,1

CRXCLK

TQ9502 RX

RXD0..9

RXCLK

SYNC

RLX, RLY

2

RX, RY

2

RTX

RTY

SYNCEN

CLKPOL

RLTX

RLTY

Optical,

Coaxial, or

Twisted Pair

Interface

Out

Optical,

Coaxial, or

Twisted Pair

In

Interface

Termination

Network

Note that the fast edge rates of the TQ9303 TX bus

outputs can affect the stability of the TQ9501 PLL.

These edge rates can be effectively “slowed” by adding

some series resistance of from 90 to 250 ohms to the

TX data bus lines (TXD0..9) as shown in Figure 4.

Resistance should also be added to TXCLK to maintain

the correct timing relationship with the data lines. The

resistors should be placed near the TQ9303.

Figure 4. Adding resistance and capacitance to

the TX data bus.

TQ9303

TQ9301

In cases where the line capacitance of the bus traces is

less than 3 pF, it may also be necessary to add from

1– 2 pf of capacitance to each trace near the TQ9501.

The purpose is to slow the edge rates enough to

prevent potential undershoot from disturbing the power

supplies in the PLL circuitry of the TQ9501.

For additional information and latest specifications, see our website: www.triquint.com

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