TQ9501-MC Просмотр технического описания (PDF) - TriQuint Semiconductor

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TQ9501-MC

531/1063 Mbaud Fibre Channel Transmitter and Receiver

TriQuint Semiconductor 

TQ9501/TQ9502

Functional Description – TQ9502 Receiver

The TQ9502 consists of a clock and data recovery

circuit, a multiplexer, and a serial-to-parallel converter

block, as shown in Figure 3. The multiplexer selects

between the RX and RY inputs or the RLX and RLY

inputs. Outputs RTX, RTY, RLTX and RLTY, not shown

on Figure 3, are provided for Fly-By™ termination,

which allows termination resistors to be placed away

from the chip. The multiplexer output is selected by the

LOOPEN pin as shown in Table 1. The selected data

goes to the CDR (Clock/Data Recovery) block.

The clock and data recovery block has two modes:

clock recovery and frequency acquisition. In the clock

input, it automatically switches to the frequency

acquisition mode which causes the CDR to lock onto

the REFCLK signal. This prevents the PLL from drifting

away from the serial data rate and ensures that the

CDR will properly lock onto the input serial data when it

is reapplied.

The receiver synchronizes 1 ms after applying power,

REFCLK and data. The receiver synchronizes 200 µs

after applying valid data if power and REFCLK has

already been applied. The output of this block is latched

into the output register. When SYNCEN is high

(SYNCronization ENable), the serial-to-parallel

converter monitors the serial data for the K28.5

character. When it sees a K28.5, it realigns the 10-bit

register to the K28.5 character and drives SYNC high.

the realignment. When SYNCEN is low, SYNC is driven

low and the serial-to-parallel converter ignores the

K28.5 character.

The output register takes in the 10-bit-wide output

from the Serial-to-Parallel Converter and drives the

RXD0..9 outputs. RXD0..9 are strobed on the rising

edge of RXCLK. CLKPOL = 1 results in a longer setup

time and shorter hold time than CLKPOL = 0. The first

serial bit is placed in RXD9 and the tenth bit is placed

in RXD0.

Fibre Channel Interface

Figure 3 illustrates a typical Fibre Channel physical

layer block diagram using the TQ9501, TQ9502 and

TQ9303 chip set. The interface between the host and

ENDEC operates at 26.5625 MHz with a data width of

32-bits for the transmit path and a separate 32-bits for

the receive path. The ENDEC performs the 8b/10b

encoding and decoding; ordered set encoding and

decoding; parity checking and generation; 32-bit CRC

checking and generation; and word synchronization.

The interface between the TQ9303 and the TQ9501/

TQ9502 operates at 531.25 or 106.250 MHz with an

encoded data width of 10-bits. The serial interface

operates from 531.125 Mbaud or 1.0625 Gbaud

respectively, which is connected to an optical, coaxial

or twisted pair interface.

The clock generate block also detects SYNC going high,

and delays the phase of the output RXCLK to coincide

with the new alignment. Some bits may be lost during

For additional information on the ENDEC, please refer

to the TQ9303 data sheet.

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For additional information and latest specifications, see our website: www.triquint.com

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