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TQ9502

531/1063 Mbaud Fibre Channel Transmitter and Receiver

TriQuint Semiconductor 

TQ9501/TQ9502

Fibre Channel is optimized for predictable transfers of

large blocks of data, such as those used in file

transfers between processors (super computer,

mainframe, super-mini, etc.), storage systems (disk

and tape), and output-only devices such as laser

printers and raster scan graphics terminals.

TriQuint offers two chip sets for Fibre Channel: the

TQ9501 and TQ9502 chip set for 531.125 Mbaud and

1.0625 Gbaud, and the GA9101 and GA9102 chip set

for the 265.625 Mbaud rate.

Functional Description – TQ9501 Transmitter

The Fibre Channel protocol is implemented in

hardware, making it simple, efficient and robust. The

lower-level physical interface is decoupled from the

higher-level protocol allowing the Fibre Channel to be

configured with various topologies, including point-to-

point, multi-drop bus, ring, and cross point switch.

Fibre Channel supports distances up to 10 Km at baud

rates of 132.8125 Mbaud to 1.0625 Gbaud. Copper

media such as Coax and STP (Shielded Twisted Pair)

are used for shorter distances while fiber optic cables

are used for longer distances.

Applications for the TQ9501 and TQ9502 include serial

SCSI, IPI, HIPPI, point-to-point serial communication,

ATM and other networking applications.

Figure 1. TQ9501 Transmitter

The TQ9501 serializes a 10-bit TTL input into a

differential PECL output. The TQ9501 is composed of

an input register, a parallel-to-serial converter, a PLL

clock generator, a differential output buffer and a PECL-

to-TTL translator, as illustrated in Figure 1.

The self-contained PLL (Phase-Locked Loop) clock

generator requires no external components. It

generates an internal high-speed bit clock for the serial

output, an internal byte clock for the parallel-to-serial

converter and BYTECLK, based on REFCLK (REFerence

CLocK). BYTECLK is used by the TQ9303 ENDEC to

generate TXCLK.

TXD0..9 are latched into the input register on the rising

edge of TXCLK. The parallel-to-serial converter

serializes the data into a differential PECL buffer. TXD9

is sent first and TXD0 is sent last.

LOOPEN

TLX

TLY

TX

TY

SIG

SIGN

2

PLL Clock

Generator

Bit

Clock

Byte

Clock

Parallel-

to-Serial

Converter

10

PECL-to-TTL

Converter

RATESEL

REFCLK

(25–31.25 MHz

BYTECLK

(50–62.5 MHz

or 100–125 MH

10 TXD0..9

TXCLK

SIGDET

2

For additional information and latest specifications, see our website: www.triquint.com

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