AD7226(RevA) Просмотр технического описания (PDF) - Analog Devices

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AD7226
(Rev.:RevA)

LC2MOS Quad 8-Bit D/A Converter

Analog Devices 

AD7226

INTERFACE LOGIC INFORMATION

Address lines A0 and A1 select which DAC will accept data

from the input port. Table I shows the selection table for the

four DACs with Figure 4 showing the input control logic. When

the WR signal is LOW, the input latches of the selected DAC

are transparent and its output responds to activity on the data

bus. The data is latched into the addressed DAC latch on the

rising edge of WR. While WR is high the analog outputs remain

at the value corresponding to the data held in their respective

latches.

Table I. AD7226 Truth Table

AD7226 Control Inputs AD7226

WR A1 A0

Operation

H

X

X

L

L

L

g

L

L

L

L

H

g

L

H

L

H

L

g

H

L

L

H

H

g

H

H

No Operation Device Not Selected

DAC A Transparent

DAC A Latched

DAC B Transparent

DAC B Latched

DAC C Transparent

DAC C Latched

DAC D Transparent

DAC D Latched

L = Low State, H = High State, X = Don’t Care

Typical Performance Characteristics

(TA = 25؇C, VDD = +15 V, VSS = –5 V)

Figure 6. Channel-to-Channel Matching

Figure 4. Input Control Logic

Figure 7. Relative Accuracy vs. VREF

Figure 5. Write Cycle Timing Diagram

Figure 8. Differential Nonlinearity vs. VREF

–6–

REV. A

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