AD7720 Просмотр технического описания (PDF) - Analog Devices
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AD7720 Datasheet PDF : 16 Pages
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AD7720
TIMING CHARACTERISTICS (AVDD = +5 V ؎ 5%; DVDD = +5 V ؎ 5%; AGND = DGND = 0 V, REF2 = +2.5 V unless otherwise noted)
Parameter
fMCLK
t1
t2
t3
t4
t5
t6
t7
NOTE
Guaranteed by design.
Limit at TMIN, TMAX
(B Version)
100
15
67
0.45 × tMCLK
0.45 × tMCLK
15
10
10
20 × tMCLK
Units
kHz min
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns max
Conditions/Comments
Master Clock Frequency
12.5 MHz for Specified Performance
Master Clock Period
Master Clock Input High Time
Master Clock Input Low Time
Data Hold Time After SCLK Rising Edge
RESET Pulsewidth
RESET Low Time Before MCLK Rising
DVAL High Delay after RESET Low
TO
OUTPUT
PIN
CL
50pF
IOL
1.6mA
+1.6V
IOH
200 A
Figure 2. Load Circuit for Access Time and Bus Relinquish Time
SCLK (O)
t1
t3
DATA (O)
NOTE:
O SIGNIFIES AN OUTPUT
t2
t4
Figure 3. Data Timing
MCLK (I)
t6
RESET (I)
t5
t7
DVAL (O)
NOTE:
I SIGNIFIES AN INPUT
O SIGNIFIES AN OUTPUT
Figure 4. RESET Timing
–4–
REV. 0
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