TMC2072KHC Просмотр технического описания (PDF) - Fairchild Semiconductor

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Компоненты Описание

производитель

TMC2072KHC

Genlocking Video Digitizer

Fairchild Semiconductor 

PRODUCT SPECIFICATION

TMC2072

Details (continued)

Bit

Name

Function

Reg 06 Blank level

Read Only

7:0

BP

Blank level, as measured at the low-pass-filtered A/D output during each line’s

color back porch. For a standard video input, its decimal value will be

approximately 60 (NTSC) or 64 (PAL). [TMC22071A bits 55:48.]

Reg 07 Reserved

Reg 08 Standard and Clock Rate Select

7:6

V_STD

Video Standard. These two control bits select the incoming video standard, viz:

00 NTSC, NTSC-EIAJ (power-on default)

01 PALM (Brazil)

10 PALB,G,H,I

11 PALN (Argentina)

5:4

CK_RATE

[With bits 5:4, these bits cover all functions of TMC22071A bits 3:1.]

Pixel Clock/Sample Rate. Pixel (sample) rate selector, as follows:

00 12.27 MHz (power-on default; 525-line VGA)

01 13.5 MHz (D1 television rate)

10 14.75 MHz (625-line square-pixel VGA) TMC2072-1 only

11 15.0 MHz TMC2072-1 only

3

FREERUN

2

BPFOUT

1

DC_CLAMP

0

S_RESET

Reg 09 Lead-Lag

7:0

LEAD_LAG

Note: The 12.27 MHz pixel rate is reserved for 525-line television standards

(NTSC, PAL-M), whereas the 14.75 and 15.0 MHz rates are for 625-line

standards (all other PAL) only. Bit combinations 0x1x and 1x00 may yield stable

composite data samples, sync pulses, and pixel clock, but no useful color

subcarrier information.

Freerun vs. Genlock Operation. LOW (power-on default): Standard genlock

mode, in which the PXCK, GHSYNC, and GVSYNC lock to the incoming video’s

observed sync pattern. HIGH: GHSYNC is counted down from a free-running

PXCK, which is unrelated to the incoming video. [TMC22071A bit 26.]

Genlock Reference Signal Enable. LOW (power-on default): Loop-predicted

subcarrier phase and frequency data (GRS) are sent over CVBS during each

horizontal sync pulse. HIGH: GRS data suppressed, such that the CVBS

datastream is just the digitized incoming video signal. [TMC22071A bit 33.]

HIGH (power-on default): vertically low-pass filtered digital porch clamp enabled.

LOW: digital clamp disabled [TMC22071A bit 34, except that the TMC22071A

clamp has no vertical filter.]

Master Software Reset Control. HIGH (power-on default & self-reset state):

normal operation. LOW: Bringing this “one-shot” control low resets all internal

state machines and registers except the microprocessor control bits themselves.

The bit then sets itself high, permitting normal operation. (Because it

automatically returns to the high state, this bit will always appear as a 1 when

read through the microprocessor port.) [TMC22071A bit 0.]

Hsync Lead/lag Control (in one-pixel = two-PXCK increments). Power-on

default = 80 Hex. To advance (delay) GHSYNC and GVSYNC relative to the

video input, decrease (increase) the value. Program code 79h, with sub pixel

control = 0.5 will align the GHSYNC output with the falling sync edge of the input

video. [TMC22071A bits 24:17.]

REV. 1.0.4 6/19/01

9

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