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TMC2072

Genlocking Video Digitizer

Fairchild Semiconductor 

TMC2072

PRODUCT SPECIFICATION

Functional Description

The TMC2072, a fully integrated self-genlocking video A/D

converter, digitizes NTSC or PAL baseband composite sig-

nals. It accepts video on one of three input channels, adjusts

the gain, clamps to the back porch and digitizes the video at

a user-selectable multiple of the horizontal line frequency.

It extracts horizontal and vertical sync, measures the subcar-

rier frequency and phase, and provides these data with the

digitized composite data over an 8-bit digital video port.

Horizontal and vertical sync outputs are provided, along with

pixel clock (LDV) and twice pixel clock (PXCK).

Operating parameters are set up via a standard two-wire

microprocessor port. The chip can work with either an inter-

nal or an external voltage reference.

Fabricated in an advanced CMOS process, the TMC2072 is

housed in a 100 lead metric quad flat package. Its perfor-

mance is guaranteed from 0 to 70°C and from 4.75 to 5.25

supply volts.

Timing

The TMC2072’s A/D converter and digital signal path

operate from alternate cycles of an internally-synthesized

clock, PXCK. This 24.5 to 30 MHz clock is derived from the

incoming 20 MHz reference clock and phase-locked to the

horizontal sync tips of the incoming analog video stream.

The frequency of PXCK may be set as 1560 (NTSC VGA

square pixel), 1716 (NTSC D1), 1732 (PAL D1), or 1888 or

1920 (PAL VGA) times the incoming video line rate.

Timing of the serial microprocessor interface bus is indepen-

dent of the pixel clock and is described under the Micropro-

cessor Interface section that follows Functional Description.

Video Input

Via the microprocessor interface, the user can enable one of

the chip’s three analog video input ports. Although each port

normally anticipates a standard video signal level with

286 to 300 mV between sync tip and blank, another control

register bit allows it to be used with half-power (approxi-

mately 70% amplitude) signals. Good crosstalk isolation

accommodates active video on all three inputs simulta-

neously. The user must provide antialias filtering and proper

line termination externally.

Analog Clamp

The front-end analog clamp ensures that the input video falls

within the active range of the A/D converter. The digitized

composite video output can be clamped to the back porch by

a secondary digital clamp.

Automatic Gain Adjustment

To accommodate approximately a ±15% range in video

signal amplitudes, the TMC2072’s on-chip AGC circuit

engages for one video frame following either: 1) initial lock

after reset; 2) loss and recovery of lock while operating; or

3) setting of control bit AGCEN high by the host micropro-

cessor. The AGC operation adjusts the A/D converter’s on-

chip reference voltages until video blank causes it to output

approximately 1/4 of its full range. The chip then holds this

gain adjustment constant until a new AGC sequence is initi-

ated by AGCEN going high or by loss and recovery of video

lock. The one-frame timeout prevents the gain control from

riding gain and trying to track noise or minor variations in

signal strength.

To handle doubly-terminated and other weak video signals,

the user should set the VGAIN control bit high, thereby

boosting video gain 50% above nominal.

Analog-to-Digital Converter

The TMC2072 contains a high-performance 8-bit A/D

converter. Its gain and offset are automatically set as a part of

the automatic gain adjustment process during initial signal

acquisition, and require no user attention.

The reference voltages to the A/D converter are set up by

internal D/A converters under automatic control during

genlock acquisition. These voltages determine the gain and

offset of the A/D converter with respect to the video level

presented at its input.

Low-Pass Filter

The digitized composite video stream is digitally low-pass

filtered to remove chrominance components from the sync

separator. Filtering provides robust operation by optimizing

the signal-to-noise ratio of the synchronizing/blanking por-

tion of the video, improving the accuracy of the back porch

blanking level detector.

A digital sync separator provides the output sync signals,

GHSYNC and GVSYNC, and times internal operations.

Horizontal Phase-Locked Loop

A phase-locked loop generates PXCK, at twice the pixel

rate. The reference signal for the horizontal phase-locked

loop is generated by the Direct Digital Synthesizer (DDS).

The DDS output is constructed with an internal D/A con-

verter and is output from the TMC2072 via the DDS OUT

pin. This signal is passed through an external LC filter and

input to the horizontal phase-comparator.

The frequency of the DDS output is one ninth of that of

PXCK.

A 20MHz clock is required to drive the DDS. Preferably, this

may be input to the TMC2072 via CMOS levels on the CLK

IN pin. Alternately, a 20MHz crystal may be directly

connected between CLK IN and CLK OUT with tuning

capacitors to activate the internal crystal oscillator circuitry.

2

REV. 1.0.4 6/19/01

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