MSM82C54-2JS Просмотр технического описания (PDF) - Oki Electric Industry
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MSM82C54-2JS Datasheet PDF : 23 Pages
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¡ Semiconductor
MSM82C54-2RS/GS/JS
DESCRIPTION OF PIN FUNCTIONS
Pin Symbol Name Input/Output
Function
D7 - D0
Bidirectional
Data Bus
Three-state 8-bit bidirectional data bus used when writing control
Input/Output words and count value, and reading count values upon reception of
WR and RD signals from CPU.
Data transfer with the CPU is enabled when this pin is at low level.
CS
Chip Select
Input
When at high level, the data bus (D0 thru D7) is switched to high
Input
impedance state where neither writing nor reading can be executed.
Internal registers, however, remain unchanged.
RD
Read Input
Input
Data can be transferred from MSM82C54-2 to CPU when this pin is
at low level.
WR
Write Input
Input
Data can be transferred from CPU to MSM82C54-2 when this pin is
at low level.
A0, A1 Address Input
Input
One of the three internal counters or the control word register is
selected by A0/A1 combination. These two pins are normally
connected to the two lower order bits of the address bus.
CLK0 - 2 Clock Input
Input
Supply of three clock signals to the three counters incorporated in
MSM82C54-2.
GATE0 - 2 Gate Input
Input
Control of starting, interruption, and restarting of counting in the
three respective counters in accordance with the set control word
contents.
OUT0 - 2 Counter Output Output
Output of counter output wave form in accordance with the set
mode and count value.
SYSTEM INTERFACING
A1 A0
Adress Bus
Control Bus
16 bits
Data Bus
8 bits
8 bits
A1 A0 CS D7 - 0 RD WR
MSM82C54-2
Counter #0
Counter #1
Counter #2
OUT GATE CLK
OUT GATE CLK
OUT GATE CLK
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