MSM82C54-2RS Просмотр технического описания (PDF) - Oki Electric Industry
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MSM82C54-2RS Datasheet PDF : 23 Pages
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¡ Semiconductor
MSM82C54-2RS/GS/JS
AC CHARACTERISTICS
Parameter
Address Set-up Times to Falling Edge of RD
Chip Select Input Set-up Time to Falling Edge of RD
Address Hold Time from Rising Edge of RD
RD Pulse Width
Data Access Time from Falling Edge of RD
Data Access Time after Address Determination
Delay Time from Rising Edge of RD to Data Floting State
RD Recovery Time
Address Set-up Time to Falling Edge of WR
Chip Select Input Set-up Time to Falling Edge of WR
Address Hold Time from Rising Edge of WR
WR Pulse Width
Data Determination Set-up Time to Rising Edge of WR
Data Hold Time after Rising Edge of WR
WR Recovery Time
CLK Cycle Time
CLK "H" Level Width
CLK "L" Level Width
CLK Rise Time
CLK Fall Time
GATE "H" Level Width
GATE "L" Level Width
GATE Input Set-up Time before Rising Edge of CLK
GATE Input Hold Time before Rising Edge of CLK
Output Delay Time after Falling Edge of CLK
Output Delay Time after Falling Edge of GATE
CLK Rise Delay Time after Rising Edge of WR for Count Value
Loading
GATE sampling delay time after rising edge of WR for count
loading
Output Delay Time after Falling Edge of WR for Mode Set
CLK Fall Set-up Time to Falling Edge of WR for Counter Latch
Command
(VCC = 4.5 V to 5.5 V, Ta = –40°C to +85°C)
82C54-2
Symbol
Unit Conditions
Min. Max.
tAR
30
— ns
tSR
0
— ns
tRA
0
— ns
tRR
95
— ns
tRD
—
94
ns
tAD
—
184 ns
tDF
5
65 ns
tRV 165 — ns
tAW
0
— ns
tSW
0
— ns
tWA
0
— ns
tWW 95
— ns
tDW
85
— ns
tWD
0
— ns
tRV 165 — ns
tCLK 100 D.C. ns
tPWH 30
— ns
tPWL 50
— ns
tr
— 25 ns
tf
— 25 ns
tGW
50
— ns
tGL
50
— ns
tGS
40
— ns
tGH
50
— ns
tOD
—
100 ns
tODG
—
100 ns
CL = 150 pF
tWC
0
55 ns
tWG
–5
40 ns
tWO — 240 ns
tCL
–40
40
ns
Note: Timing measured at VL = 0.8 V and VH = 2.2 V for both inputs and outputs.
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