TLP558 Просмотр технического описания (PDF) - Toshiba
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TLP558 Datasheet PDF : 6 Pages
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TLP558
Switching Characteristics (unless otherwise specified, VCC = 4.5 to 20V, Ta = 25°C)
Characteristic
Propagation delay time to
logic high output
(Note 1)
Propagation delay time to
logic low output
(Note 1)
Output rise time (10-90%)
Output fall time (90-10%)
Common mode transient
immunity at logic high
output
(Note 2)
Common mode transient
immunity at logic low
output
(Note 2)
Symbol
Test
Circuit
Test Condition
tpLH
IF = 3→ 0 mA
tpHL
tr
tf
CMH
CML
1 IF = 0→ 3 mA
IF = 3→ 0 mA, VCC = 5 V
IF = 0→ 3 mA, VCC = 5 V
IF = 0 mA, VCM = 50 V
VO (Min) = 2 V
3
IF = 1.6 mA, VCM = 50 V
VO (Max) = 0.8 V
Min
Typ.
Max
Unit
―
250
400
ns
―
270
―
35
―
20
1000
―
400
ns
75
ns
75
ns
―
V / μs
-1000
―
―
V / μs
Note: All typical values are at Ta = 25 °C, VCC = 5 V
Note: A ceramic capacitor (0.1 μF) should be connected from pin 8 to pin 5 to stabilize the operation of the high gain
linear amplifier. Failure to provide the bypassing may impair the switching property. The total lead length
between capacitor and coupler should not exceed 1cm.
Note 1: The tpLH propagation delay is measured from the 50 % point on the trailing edge of the input pulse to the 1.3
V point on the leading edge of the output pulse. The tpHL propagation delay is measured from the 50 % point
on the leading edge of the input pulse to the 1.3 V point on the trailing edge of the output pulse.
Note 2: CML is the maximum rate of fall of the common mode voltage that can be sustained with the output voltage in
the logic low state (VO < 0.8 V).
CMH is the maximum rate of rise of the common mode voltage that can be sustained with the output voltage
in the logic state (VO > 2.0 V).
© 2019
4
Toshiba Electronic Devices & Storage Corporation
2019-06-24
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