LH5164A Просмотр технического описания (PDF) - Sharp Electronics

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производитель

LH5164A

CMOS 64K (8K × 8) Static RAM

Sharp Electronics 

LH5164A/AH

CMOS 64K (8K × 8) Static RAM

A0 - A12

CE1

tWC

tAW

tCW

(NOTE 2)

tCW

tWR (NOTE 4)

tWR

CE2

WE

DOUT

tAS

(NOTE 3)

(NOTE 5)

(NOTE 7)

DIN

OE = 'LOW'

tWP

tWR

(NOTE 1)

tWZ

HIGH-Z

tDW

tOW

(NOTE 6)

tDH

DATA VALID

NOTES:

1. The writing occurs during an overlapping period of CE1 = 'LOW,' CE2 = 'HIGH,' and WE = 'LOW' (tWP).

2. tCW is defined as the time from the last occuring transition, either CE1 LOW transition or CE2 HIGH transition,

to the time when the writing is finished.

3. tAS is defined as the time from address change to writing start.

4. tWR is defined as the time from writing finish to address change.

5. If CE1 LOW transition or CE2 HIGH transition occurs at the same time or after WE LOW transition, the

outputs will remain high-impedance.

6. If CE1 HIGH transition or CE2 LOW transition occurs at the same time or before WE HIGH transition, the

outputs will remain high-impedance.

7. While I/O pins are in the output state, input signals with the opposite logic level must not be applied.

Figure 7. Write Cycle 2

5164A-5

8

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