LH5164A Просмотр технического описания (PDF) - Sharp Electronics

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LH5164A

CMOS 64K (8K × 8) Static RAM

Sharp Electronics 

LH5164A/AH

CMOS 64K (8K × 8) Static RAM

CE1 CONTROL (NOTE)

DATA RETENTION MODE

VCC

tCDR

tR

4.5 V

2.2 V

VCCDR

CE1

0V

CE1 ≥ VCCDR - 0.2 V

CE2 CONTROL

VCC

CE2

4.5 V

DATA RETENTION MODE

tCDR

tR

VCCDR

0.8 V

0V

CE2 0.2 V

NOTE: To control data hold at CE1, fix the input level of CE2 between VCCDR to VCCDR - 0.2 V or 0 V to 0.2 V

during the data retention mode.

Figure 4. Low Voltage Data Retention

5164A-6

A0 - A12

CE1

CE2

OE

I/O1 - I/O8

NOTE: WE = 'HIGH.'

6

tRC

tAA

tACE1

tLZ1

tACE2

tHZ1

tLZ2

tOE

tOLZ

tHZ2

tOHZ

DATA VALID

tOH

Figure 5. Read Cycle

5164A-3

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