CDP1826C Просмотр технического описания (PDF) - Intersil

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Компоненты Описание

производитель

CDP1826C

CMOS 64-Word x 8-Bit Static RAM

Intersil 

A0 - A5

CDP1826C

HIGH ORDER

ADDRESS BYTE

LOW ORDER ADDRESS BYTE

tAA

MRD

CS1 • CS2

tAC

VALID CHIP SELECT

tRHZ

tSHZ

BUS

HIGH IMPEDANCE

tAM

VALID DATA

FIGURE 5. TIMING WAVEFORMS FOR READ-CYCLE 2 (TPA HIGH)

Dynamic Electrical Specifications At TA = -40 to +85oC, VDD = 5V ± 5%,Input tR, tF = 10ns; CL = 50pF and 1 TTL Load

LIMITS

CDP1826C

PARAMETER

(NOTE 1)

MIN

(NOTE 2)

TYP

MAX

UNITS

WRITE - CYCLE TIMES (FIGURES 6 AND 7)

Address to TPA Setup, High Byte

tASH

100

-

-

ns

Address to TPA Hold

tAH

100

-

-

ns

Address Setup, Low Byte

TASL

500

250

-

ns

TPA Pulse Width

tPAW

200

-

-

ns

Chip Select Setup

tCS

700

350

-

ns

Write Pulse Width

tWW

300

200

-

ns

Write Recovery

tWR

100

-

-

ns

Data Setup

tDS

400

200

-

ns

Data Hold from End of MWR

tDH1

100

50

-

ns

Data Hold from End of Chip Select

tDH2

125

50

-

ns

NOTES:

1. Time required by a limit device to allow tor the indicated function.

2. Typical values are for TA = 25oC and nominal VDD.

6-53

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