HT62L256 Просмотр технического описания (PDF) - Holtek Semiconductor
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HT62L256 Datasheet PDF : 10 Pages
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Preliminary
A.C. Test Conditions
Item
Input Pulse Level
Input Rise and Fall Time
Input and Output Timing Reference Level
Output Load
0V to 3V
5ns
1.5V
See figures below
Conditions
HT62L256
+ 1 .5 V
1 .8 k W
I/O
990W
100p.
+ 1 .5 V
1 .8 k W
I/O
990W
5p.
* In c lu d in g s c o p e a n d jig
O u tp u t lo a d
* In c lu d in g s c o p e a n d jig
O u tp u t lo a d fo r
tC L Z , tO L Z , tC H Z , tW H Z a n d tO W
Functional Description
Operation truth table
CS
OE
H
X
L
H
L
L
L
X
WE
Mode
D0~D7
X
Standby
High-Z
H
Output Disable
High-Z
H
Read
Dout
L
Write
Din
Data retention characteristics
Symbol
Parameter
VDR
VDD for Data Retention
ICCDR
tCDR
tR
Data Retention Current
Chip Disable Data Retention Time
Operation Recovery Time
Conditions
CS ³ VDD-0.2V
VIN ³ VDD-0.2V or VIN£0.2V
CS ³ VDD-0.2V
VIN ³ VDD-0.2V or VIN£0.2V
See retention timing
See retention timing
Min.
2.0
¾
0
tRC*
Ta=-40°C to 85°C
Max.
Unit
3.3
V
2
mA
¾
ns
¾
ns
Low VDD data retention timing
V DD
3 .0 V
3 .0 V
V D D ³ 2 .0 V
tC D R
tR
CS
V IH
V IH
C S ³ V D D -0 .2 V
Rev. 0.00
4
August 15, 2002
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