LG1600KXH Просмотр технического описания (PDF) - Agere -> LSI Corporation

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LG1600KXH

Clock and Data Regenerator

Agere -> LSI Corporation 

LG1600KXH Clock and Data Regenerator

Test Circuit

Data Sheet

June 1999

+

500 kΩ

ALTERNATIVE

V–TH

51

OPTIONAL

THRESHOLD

CONTROL

50 Ω

50 Ω OPTIONAL

Ca > 0.1 µF/fB

+

VSS 5.2 V

V–FB

48

V+OUT

V–OUT

43 38

VSS

35

50 Ω

1 kΩ

0.047 µF

25 kΩ

0.047 µF

V–IN 55

V+IN 60

50 Ω

50 Ω

V+FB

0.047 µF

65 1 kΩ

50 Ω

25 kΩ

0.047 µF

0.047 µF

DQ

D

0°

FREQ. &

PHASE 90°

DETECT.

VCO

OPTIONAL

Cb > 100 pF/fB

31 V+CLKO

26 V–CLKO

50 Ω

DATA

GENERATOR

7

VREF

9

CEXT

11

REXT

LOOP CONTROL &

SIGNAL DETECT

0.047 µF

14

LOS

VLOS

CX

OPTIONAL

(SEE TEXT)

RX = 140 Ω

REQUIRED

10 kΩ

VDD

+

5V

50 Ω

12-3234(F)r.4

Notes:

Resistor RX determines the PLL bandwidth and is required for normal operation. The recommended value is 140 Ω for optimal jitter transfer per-

formance. Capacitor CX is optional and can be used to increase the damping of the PLL in critical applications.

The outputs may be either ac coupled, as indicated, or dc terminated into 50 Ω. In the first case, good output return loss can be obtained. The

latter configuration provides a 0 mV to –800 mV output swing for easy interface to dc-coupled circuits.

Figure 10. LG1600KXH Typical Test Circuit

10

Lucent Technologies Inc.

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