TJA1021T Просмотр технического описания (PDF) - NXP Semiconductors.
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TJA1021T Datasheet PDF : 25 Pages
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NXP Semiconductors
TJA1021
LIN 2.1/SAE J2602 transceiver
6. Pinning information
6.1 Pinning
RXD 1
SLP_N 2
WAKE_N 3
TXD 4
8 INH
7 VBAT
TJA1021T
6 LIN
5 GND
015aaa231
a. TJA1021T/10; TJA1021T/20: SO8
Fig 2. Pin configuration diagrams
terminal 1
index area
RXD 1
SLP_N 2
WAKE_N 3
TXD 4
TJA1021TK
8 INH
7 VBAT
6 LIN
5 GND
015aaa232
Transparent top view
b. TJA1021TK/10; TJA1021TK/20:
HVSON8
6.2 Pin description
Table 3. Pin description
Symbol
Pin
Description
RXD
1
receive data output (open-drain); active LOW after a wake-up event
SLP_N
2
sleep control input (active LOW); controls inhibit output; resets
wake-up source flag on TXD and wake-up request on RXD
WAKE_N
3
local wake-up input (active LOW); negative edge triggered
TXD
4
transmit data input; active LOW output after a local wake-up event
GND
5[1]
ground
LIN
6
LIN bus line input/output
VBAT
INH
7
battery supply voltage
8
battery related inhibit output for controlling an external voltage
regulator; active HIGH after a wake-up event
[1] HVSON8 package die supply ground is connected to both the GND pin and the exposed center pad. The
GND pin must be soldered to board ground. For enhanced thermal and electrical performance, it is
recommended that the exposed center pad also be soldered to board ground.
TJA1021
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 30 December 2010
© NXP B.V. 2010. All rights reserved.
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