TH8061 Просмотр технического описания (PDF) - Melexis Microelectronic Systems
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TH8061 Datasheet PDF : 36 Pages
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TH8061
Voltage Regulator with integrated LIN Transceiver
2.4 Dynamic Characteristics
7V ≤ VSUP ≤ 18V, -40°C ≤ TA ≤ 125°C, unless otherwise specified
Parameter
Symbol
Condition
Min
Typ
Max Unit
RESET
Reset time
Reset rising time [1]
Debouncing time BUS [1]
Wake up time
tRes
trr
tdeb_BUS
twake_BUS
70
100
140 ms
3.0
7.5
15 µs
1.5
2.8
4.0 µs
25
60
120 µs
General LIN BUS parameter
Transmit propagation delay
TxD -> BUS [2] [3]
Symmetry of propagation delay
BUS -> RxD [2]
tdr_TXD,
tdf_TXD
tdsym_TXD
RL/CL at BUS
1kΩ/1nF
660Ω/6.8nF
500Ω/10nF
tdr_TXD - tdf_TXD
4
µs
-2
2
µs
Receiver propagation delay
BUS -> RxD [2] [3]
Symmetry of propagation delay
TxD -> BUS [2]
tdr_RXD
tdf_RXD
tdsym_RXD
CL(RXD) = 50pF
tdr_RXD - tdf_RXD
6
µs
-2
2
µs
Slew rate BUS rising edge [1]
Slew rate BUS falling edge [1]
dV/dTrise
dV/dTfall
20% ≤ VBUS ≤ 80%
CBUS = 100 pF
20% ≤ VBUS ≤ 80%
100pF ≤ CBUS ≤ 10nF
1.0
1.7
2.5 V/µs
-2.5
-1.7
-1.0 V/µs
LIN BUS parameter according to LIN Spec. Rev. 1.3
Slope time, transition from recessive to
dominant [2] [3]
tsdom
VSUP = 8 V
RL= 500Ω / CL=10nF
VSUP = 18 V
RL= 500Ω / CL=10nF
Slope time, transition from dominant to
recessive [2] [3]
VSUP = 8 V
tsrec
RL= 500Ω / CL=10nF
VSUP = 18 V
RL= 500Ω / CL=10nF
Slope time symmetry
VSUP = 8 V
RL= 500Ω / CL=10nF
-7
tssym
Tssym = tsdom - tsrec
VSUP = 18 V
RL= 500Ω / CL=10nF
-5
Tssym = tsdom - tsrec
12
µs
18
12
µs
18
1
µs
5
TH8061 – Datasheet
3901008061
Page 8 of 36
June 2004
Rev 007
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