TFRA08C13 OCTAL T1/E1 Framer
Preliminary Data Sheet
October 2000
Electrical Characteristics
Logic Interface Characteristics
Table 188. Logic Interface Characteristics (TA = –40 °C to +85 °C, VDD = 3.3 V ± 5%, VSS = 0)
Parameter
Input Leakage Current
All Inputs Except Pulled-
Up and Pulled-Down Pins
Pulled-Up Pins
Pulled-Down Pins
Output Voltage:
Low
High
Input Capacitance
Load Capacitance:
All Outputs Except D[7:0]
D[7:0]
Symbol
IL
ILPU
ILPD
VOL
VOH
CI
CL
CL
Test Conditions
—
—
—
IOL = – 5.0 mA*
IOH = 5.0 mA†
—
—
—
Min
—
—
—
0
VDD – 1.0
—
—
—
Max
±10
80
185
0.5
VDD
3.0
50
100
* Sinking.
† Sourcing.
Notes:
All buffers use CMOS levels.
All inputs are driven between 2.4 V and 0.4 V.
An internal pull-up is provided on the 3-STATE, RESET, DS1/CEPT, MPMODE, CS, MPCK, TDI, TCK, and TMS pins.
An internal pull-down is provided on the TRST pin.
Unit
µA
µA
µA
V
V
pF
pF
pF
Power Supply Bypassing
External bypassing is required for each power supply pin. A 0.1 µF capacitor must be connected between each
VDD and VSS, between VDDD and VSSD, and between VDDA and VSSA. The VSS, VSSD, and VSSA planes should be
separated, joining at a single point near the external ground connection. The need to reduce high-frequency cou-
pling into the analog supply (VDDA) and quiet digital supply (VDDD) may require inductive beads to be inserted
between these lines and the 3.3 V power plane.
Capacitors used for power supply bypassing should be placed as close as possible to the device pins.
186
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