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TFRA08C13

OCTAL T1/E1 Framer

Agere -> LSI Corporation 

Preliminary Data Sheet

October 2000

TFRA08C13 OCTAL T1/E1 Framer

FDL Parameter/Control Registers ((A00—A0E); (A20—A2E); (B00—B0E);

(B20—B2E) (C00—C0E); (C20—C2E); (D00—D0E); (D20—D2E)) (continued)

Table 168. FDL Transmitter Configuration Control Register (FDL_PR3) (A03; A23; B03; B23; C03; C23; D03;

D23)

Bit

0—5

61

71

Symbol

Description

FTIL0—FTIL5

FTABT

FTFC

FDL Transmitter Interrupt Level. These bits specify the minimum number of empty

positions in the transmit FIFO which triggers a transmitter-empty (FTEM) interrupt.

Encoding is in binary; bit 0 is the least significant bit. A code of 001010 will generate an

interrupt when the transmit FIFO has ten or more empty locations. The code 000000

generates an interrupt when the transmit FIFO is empty. The number of empty transmit

FIFO locations is obtained by reading the transmit FDL status register FDL_SR1.

FDL Transmitter Abort. FTABT = 1 forces the transmit FDL unit to abort the frame at the

last user data byte waiting for transmission. When the transmitter reads the byte tagged

with FTABT, the abort sequence (01111111) is transmitted in its place. A full byte is guar-

anteed to be transmitted. Once set for a specific data byte, the internal FTABT status

cannot be cleared by writing to this bit. Clearing this bit has no effect on a previously writ-

ten FTABT. The last value written to FTABT is available for reading.

FDL Transmitter Frame Complete. FTFC = 1 forces the transmit FDL unit to terminate

the frame normally after the last user data byte is written to the transmit FIFO. The CRC

sequence and a closing flag are appended. FTFC should be set to 1 within 1 ms of writ-

ing the last byte of the frame in the transmit FIFO. When the transmit FIFO is empty, writ-

ing two data bytes to the FIFO before setting FTCF provides a minimum of 1 ms to write

FTFC = 1. Once set for a specific data byte, the internal FTFC status bit cannot be

cleared by writing to this bit. Clearing this bit has no effect on a previously written FTFC.

The last value written to FTFC is available for reading.

1. Do not set FTABT = 1 and FTFC = 1 at the same time.

Table 169. FDL Transmitter FIFO Register (FDL_PR4) (A04; A24; B04; B24; C04; C24; D04; D24)

Bit

0—7

Symbol

Description

FTD0—FTD7 FDL Transmit Data. The user data to be transmitted via the FDL block are loaded

through this register.

Table 170. FDL Transmitter Idle Character Register (FDL_PR5) (A05; A25; B05; B25; C05; C25; D05; D25)

Bit

0—7

Symbol

Description

FTIC0—FTIC7 FDL Transmitter Idle Character. This character is used only in transparent mode (regis-

ter FDL_PR9 bit 6 = 1). When the pattern match bit (register FDL_PR9 bit 5) is set to 1,

the FDL transmit unit sends this character whenever the transmit FIFO is empty. The

default is to send the ones idle character, but any character can be programmed by the

user.

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171

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