TEA5768HL Просмотр технического описания (PDF) - Philips Electronics

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TEA5768HL

Low-power FM stereo radio for handheld applications

Philips Electronics 

Philips Semiconductors

Low-power FM stereo radio for

handheld applications

Product specification

TEA5768HL

7.7 IF filter

Fully integrated IF filter.

7.8 FM demodulator

The FM quadrature demodulator has an integrated

resonator to perform the phase shift of the IF signal.

7.9 Level voltage generator and analog-to-digital

converter

The FM IF analog level voltage is converted to 4 bits digital

data and output via the I2C-bus.

7.10 IF counter

The IF counter outputs a 7-bit count result via the I2C-bus.

7.11 Soft mute

The low-pass filtered level voltage drives the soft mute

attenuator at low RF input levels. The soft mute function

can be switched off via the I2C-bus.

7.12 MPX decoder

The PLL stereo decoder is adjustment-free. The stereo

decoder can be switched to mono via the I2C-bus.

7.13 Signal dependent mono to stereo blend

With a decreasing RF input level the MPX decoder blends

from stereo to mono to limit the output noise. The

continuous mono to stereo blend can also be programmed

via the I2C-bus to an RF level depending switched mono to

stereo transition. Stereo Noise Cancelling (SNC) can be

switched off via the I2C-bus.

7.14 Signal dependent AF response

The audio bandwidth will be reduced with a decreasing RF

input level. This function can be switched off via the

I2C-bus.

7.15 Software programmable ports

Two software programmable ports (open-collector) can be

addressed via the I2C-bus.

The port 1 (pin SWPORT1) function can be changed with

write data byte 4 bit 0 (see Table 13). Pin SWPORT1 is

then output for the ready flag of read byte 1.

8 I2C-BUS AND BUS-CONTROLLED FUNCTIONS

8.1 I2C-bus specification

Information about the I2C-bus can be found in the brochure

“The I2C-bus and how to use it” (order number

9398 393 40011).

The standard I2C-bus specification is expanded by the

following definitions.

IC address C0: 1100000.

Structure of the I2C-bus logic: slave transceiver.

Subaddresses are not used.

The maximum LOW-level input and the minimum

HIGH-level input are specified to 0.2VCCD and 0.45VCCD

respectively.

The pin BUSMODE must be connected to ground.

Before any READ or WRITE operation the pin

BUSENABLE has to be HIGH for at least 10 µs.

Note: The bus operates at a maximum clock frequency of

400 kHz. It is not allowed to connect the IC to a bus

operating at a higher clock rate.

8.1.1 DATA TRANSFER

Data sequence: address, byte 1, byte 2, byte 3, byte 4 and

byte 5 (the data transfer has to be in this order). The

LSB = 0 of the address indicates a WRITE operation to the

TEA5768HL.

Bit 7 of each byte is considered as the MSB and has to be

transferred as the first bit of the byte.

The data becomes valid bitwise at the appropriate falling

edge of the clock. A STOP condition after any byte can

shorten transmission times.

When writing to the transceiver by using the STOP

condition before completion of the whole transfer:

• The remaining bytes will contain the old information

• If the transfer of a byte is not completed, the new bits will

be used, but a new tuning cycle will not be started.

The IC can be switched into a low current standby mode

with the standby bit; the bus is then still active. The

standby current can be reduced by deactivating the bus

interface (pin BUSENABLE LOW). If the bus interface is

deactivated (pin BUSENABLE LOW) without the standby

mode being programmed, the IC maintains normal

operation, but is isolated from the bus lines.

2004 Sep 13

8

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