TEA5767HL Просмотр технического описания (PDF) - Philips Electronics

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TEA5767HL

Low-power FM stereo radio for handheld applications

Philips Electronics 

Philips Semiconductors

Low-power FM stereo radio for

handheld applications

Product specification

TEA5767HL

7.7 IF filter

Fully integrated IF filter.

7.8 FM demodulator

The FM quadrature demodulator has an integrated

resonator to perform the phase shift of the IF signal.

7.9 Level voltage generator and analog-to-digital

converter

The FM IF analog level voltage is converted to 4 bits digital

data and output via the 3-wire bus.

7.10 IF counter

The IF counter outputs a 7-bit count result via the 3-wire

bus.

7.11 Soft mute

The low-pass filtered level voltage drives the soft mute

attenuator at low RF input levels. The soft mute function

can be switched off via the 3-wire bus.

7.12 MPX decoder

The PLL stereo decoder is adjustment-free. The stereo

decoder can be switched to mono via the 3-wire bus.

7.13 Signal dependent mono to stereo blend

With a decreasing RF input level the MPX decoder blends

from stereo to mono to limit the output noise. The

continuous mono to stereo blend can also be programmed

via the 3-wire bus to an RF level depending switched mono

to stereo transition. Stereo Noise Cancelling (SNC) can be

switched off via the 3-wire bus.

7.14 Signal dependent AF response

The audio bandwidth will be reduced with a decreasing RF

input level. This function can be switched off via the 3-wire

bus.

7.15 Software programmable ports

Two software programmable ports (open-collector) can be

addressed via the 3-wire bus.

The port 1 (pin SWPORT1) function can be changed with

write data byte 4 bit 0 (see Table 10). Pin SWPORT1 is

then output for the ready flag of read byte 1.

8 3-WIRE BUS AND BUS-CONTROLLED

FUNCTIONS

8.1 3-wire bus specification

The 3-wire bus controls the write/read, clock and data lines

and operates at a maximum clock frequency of 400 kHz.

Before any READ or WRITE operation the pin

BUSENABLE has to be HIGH for at least 10 µs.

Hint: By using the standby bit the IC can be switched into

a low current standby mode. In standby mode the IC must

be in the WRITE mode. When the IC is switched to READ

mode, during standby, the IC will hold the data line down.

The standby current can be reduced by deactivating the

bus interface (pin BUSENABLE LOW). If the bus interface

is deactivated (pin BUSENABLE LOW) without the

standby mode being programmed, the IC maintains

normal operation, but is isolated from the clock and data

line.

8.1.1 DATA TRANSFER

Data sequence: byte 1, byte 2, byte 3, byte 4 and byte 5

(the data transfer has to be in this order).

A positive edge at pin WRITE/READ enables the data

transfer into the IC. The data has to be stable at the

positive edge of the clock. Data may change while the

clock is LOW and is written into the IC on the positive edge

of the clock. Data transfer can be stopped after the

transmission of new tuning information with the first two

bytes or after each following byte.

A negative edge at pin WRITE/READ enables the data

transfer from the IC. The WRITE/READ pin changes while

the clock is LOW. With the negative edge at

pin WRITE/READ the MSB of the first byte occurs at

pin DATA.

The bits are shifted on the negative clock edge to pin

DATA and can be read on the positive edge.

To do two consecutive read or write actions,

pin WRITE/READ has to be toggled for at least one clock

period. When a search tuning request is sent, the IC

autonomously starts searching the FM band; the search

direction and search stop level can be selected. When a

station with a field-strength equal to or greater than the

stop level is found, the tuning system stops and the ready

flag bit is set to HIGH. When, during search, a band limit is

reached, the tuning system stops at the band limit and the

band limit flag bit is set to HIGH. The ready flag is also set

to HIGH in this case.

2004 Sep 13

8

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