TDA8024T/C1 Просмотр технического описания (PDF) - NXP Semiconductors.

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производитель

TDA8024T/C1

Standard smart card interface

NXP Semiconductors. 

NXP Semiconductors

TDA8024

Standard smart card interface

7.2 Pin description

Table 3. Pin description

Symbol

Pin

Type

CLKDIV1

1

I

CLKDIV2

2

I

5V/3V

3

I

PGND

S2

4

S

5

I/O

VDDP

S1

6

S

7

I/O

VUP

8

I/O

PRES

9

I

PRES

10

I

I/O

AUX2

AUX1

CGND

CLK

RST

VCC

PORADJ

11

I/O

12

I/O

13

I/O

14

S

15

I/O

16

O

17

S

18

I

CMDVCC

RSTIN

VDD

GND

OFF

XTAL1

19

I

20

I

21

S

22

S

23

O

24

I

Description

CLK frequency selection input 1

CLK frequency selection input 2

card supply voltage selection input; VCC = 5 V (HIGH) or

VCC = 3 V (LOW)

DC-to-DC converter power supply ground

DC-to-DC converter capacitor; connected between pins S1

and S2; C = 100 nF with ESR < 100 m

DC-to-DC converter power supply voltage

DC-to-DC converter capacitor; connected between pins S1

and S2; C = 100 nF with ESR < 100 m

DC-to-DC converter output decoupling capacitor connection;

C = 100 nF with ESR < 100 m must be connected between

VUP and PGND

card presence contact input (active LOW); if PRES or

PRES is active, the card is considered ‘present’ and a

built-in debounce feature of 8 ms (typ.) is activated

card presence contact input (active HIGH); if PRES or

PRES is active, the card is considered ‘present’ and a

built-in debounce feature of 8 ms (typ.) is activated

data line to/from card reader contact C7; integrated 11 k

pull-up resistor to VCC

data line to/from card reader contact C8; integrated 11 k

pull-up resistor to VCC

data line to/from card reader contact C4; integrated 11 k

pull-up resistor to VCC

card signal ground

card clock to/from card reader contact C3

card reset output from card reader contact C2

card supply voltage to card reader contact C1; decoupled to

CGND via 2  100 nF or 100 + 220 nF capacitors with ESR

< 100 m[1]

Power-on reset threshold adjustment input for changing the

reset threshold with an external resistor bridge; doubles the

width of the POR pulse when used; this pin is not connected

for the TDA8024AT

input from the host to start activation sequence (active LOW)

card reset input from the host

supply voltage

ground

NMOS interrupt output to the host (active LOW); 20 k

integrated pull-up resistor to VDD

crystal connection or input for external clock

TDA8024

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 4.0 — 3 June 2016

© NXP Semiconductors N.V. 2016. All rights reserved.

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