7025ERPQI45 Просмотр технического описания (PDF) - MAXWELL TECHNOLOGIES
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7025ERPQI45 Datasheet PDF : 20 Pages
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(8K x 16-Bit) Dual Port RAM High-Speed CMOS
7025E
TABLE 8. 7025E AC ELECTRICAL CHARACTERISTICS FOR WRITE MASTER/SLAVE CONFIGURATION
(VCC = 5V ± 10%, VSS = 0V, TA = -55 TO 125 °C)
PARAMETER
SYMBOL
MIN
MAX
UNIT
For Master Only
BUSY Access Time to Address Match
-35
-45
tBAA
ns
--
35
--
35
BUSY Disable Time to Address Not Matched
-35
-45
tBDA
ns
--
30
--
30
BUSY Access Time to Chip Select Low
-35
-45
tBAC
ns
--
30
--
30
BUSY Disable Time to Chip Select High
-35
-45
Write Pulse to Data Delay 1
-35
-45
Write Data Valid to Read Data Delay 1
-35
-45
Arbitration Priority Setup Time 2
-35
-45
tBDC
ns
--
25
--
25
tWDD
ns
--
60
--
70
tDDD
ns
--
45
--
55
tAPS
5
5
ns
--
--
BUSY Disable to Valid Data
-35
-45
For Slave Only
Write to BUSY Input 4
Write Hold after BUSY 5
Write Pulse to Data Delay 1
-35
-45
Write Data Valid to Read Data Delay 1
-35
-45
tBDD
ns
--
3
--
3
tWB
0
--
ns
tWH
25
--
ns
tWDD
ns
--
60
--
70
tDDD
ns
--
45
--
55
1. Port to port timing delay through RAM cells from writing port to reading port.
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD - tWP (actual) or tDDD - tWD (actual).
4. To ensure that the write cycle is inhibited during contention.
5. To ensure that a write cycle is completed after contention.
1000586
12.19.01 Rev 2
All data sheets are subject to change without notice 6
©2001 Maxwell Technologies
All rights reserved.
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