TC7126 Просмотр технического описания (PDF) - Microchip Technology
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TC7126 Datasheet PDF : 26 Pages
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3.0 DETAILED DESCRIPTION
(All Pin Designations Refer to 40-Pin PDIP.)
3.1 Dual Slope Conversion Principles
The TC7126A is a dual slope, integrating analog-to-
digital converter. An understanding of the dual slope
conversion technique will aid in following the detailed
TC7126/A operation theory.
The conventional dual slope converter measurement
cycle has two distinct phases:
• Input Signal Integration
• Reference Voltage Integration (De-integration)
The input signal being converted is integrated for a
fixed time period (TSI). Time is measured by counting
clock pulses. An opposite polarity constant reference
voltage is then integrated until the integrator output
voltage returns to zero. The reference integration time
is directly proportional to the input signal (TRI) (see
Figure ).
Analog
Input
Signal
Integrator
–
+
Comparator
–
+
REF
Voltage
Switch
Driver
Phase
Control
Polarity Control
Control
Logic
Clock
Display
Counter
VIN » VREF
VIN » 1.2 VREF
Fixed Variable
Signal Reference
Integrate Integrate
Time Time
FIGURE 3-1:
Basic Dual Slope Converter
In a simple dual slope converter, a complete conver-
sion requires the integrator output to “ramp-up” and
“ramp-down.”
A simple mathematical equation relates the input
signal, reference voltage and integration time:
TC7126/A
EQUATION 3-1:
Where:
∫1
RC
TSI
0
VIN(t)dt
=
VRTRI
RC
VR = Reference voltage
TSI = Signal integration time (fixed)
TRI = Reference voltage integration time (variable)
For a constant VIN:
EQUATION 3-2:
VIN
=
VR
T---R----I
TSI
The dual slope converter accuracy is unrelated to the
integrating resistor and capacitor values, as long as
they are stable during a measurement cycle. Noise
immunity is an inherent benefit. Noise spikes are inte-
grated or averaged to zero during integration periods.
Integrating ADCs are immune to the large conversion
errors that plague successive approximation convert-
ers in high noise environments. Interfering signals with
frequency components at multiples of the averaging
period will be attenuated. Integrating ADCs commonly
operate with the signal integration period set to a
multiple of the 50Hz/60Hz power line period (see
Figure 3-2).
30
20
10
0
0.1/t
t = Measurement Period
1/t
10/t
Input Frequency
FIGURE 3-2:
Normal Mode Rejection of
Dual Slope Converter
© 2006 Microchip Technology Inc.
DS21458C-page 9
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