TB62726AFG Просмотр технического описания (PDF) - Toshiba

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TB62726AFG

TOSHIBA Bi-CMOS Integrated Circuit Silicon Monolithic

Toshiba 

Timing Diagram

n = 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

CLOCK

SERIAL-IN

LATCH

ENABLE

OUT0

OUT1

OUT3

TB62726ANG/AFG

3.3 V/5 V

0V

3.3 V/5 V

0V

3.3 V/5 V

0V

3.3 V/5 V

0V

On

Off

On

Off

On

Off

OUT15

SERIAL-OUT

On

Off

3.3 V/5 V

0V

Warning: Latch circuit is leveled-latch circuit. Be careful because it is not triggered-latch circuit.

Note 2:

The latches circuit holds data by pulling the LATCH terminal Low.

And, when LATCH terminal is a High level, latch circuit doesn’t hold data, and it passes from the input to

the output.

When ENABLE terminal is a Low level, output terminal OUT0 to OUT15 respond to the data, and on

and off does.

And, when ENABLE terminal is a High level, it offs with the output terminal regardless of the data.

3

2006-06-14

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